Commit 10543365 authored by Mohamad Haj Yahia's avatar Mohamad Haj Yahia Committed by Saeed Mahameed
Browse files

net/mlx5: Add support to s-tag in mlx5 firmware interface 



Add svlan_tag and rename vlan_tag to cvlan_tag in flow table entry
match param.

Signed-off-by: default avatarMohamad Haj Yahia <mohamad@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
Signed-off-by: default avatarLeon Romanovsky <leonro@mellanox.com>
parent ee7f1220

drivers/infiniband/hw/mlx5/main.c

+2 −2
Original line number Diff line number Diff line
@@ -1704,9 +1704,9 @@ static int parse_flow_attr(u32 *match_c, u32 *match_v, 


		if (ib_spec->eth.mask.vlan_tag) {

			MLX5_SET(fte_match_set_lyr_2_4, headers_c,

				 vlan_tag, 1);

				 cvlan_tag, 1);

			MLX5_SET(fte_match_set_lyr_2_4, headers_v,

				 vlan_tag, 1);

				 cvlan_tag, 1);



			MLX5_SET(fte_match_set_lyr_2_4, headers_c,

				 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));

drivers/net/ethernet/mellanox/mlx5/core/en_fs.c

+5 −5
Original line number Diff line number Diff line
@@ -172,7 +172,7 @@ static int __mlx5e_add_vlan_rule(struct mlx5e_priv *priv, 
	dest.ft = priv->fs.l2.ft.t;



	spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;

	MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);



	switch (rule_type) {

	case MLX5E_VLAN_RULE_TYPE_UNTAGGED:
@@ -180,11 +180,11 @@ static int __mlx5e_add_vlan_rule(struct mlx5e_priv *priv, 
		break;

	case MLX5E_VLAN_RULE_TYPE_ANY_VID:

		rule_p = &priv->fs.vlan.any_vlan_rule;

		MLX5_SET(fte_match_param, spec->match_value, outer_headers.vlan_tag, 1);

		MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 1);

		break;

	default: /* MLX5E_VLAN_RULE_TYPE_MATCH_VID */

		rule_p = &priv->fs.vlan.active_vlans_rule[vid];

		MLX5_SET(fte_match_param, spec->match_value, outer_headers.vlan_tag, 1);

		MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 1);

		MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria,

				 outer_headers.first_vid);

		MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid,
@@ -991,7 +991,7 @@ static int __mlx5e_create_vlan_table_groups(struct mlx5e_flow_table *ft, u32 *in 


	memset(in, 0, inlen);

	MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);

	MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.vlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.cvlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.first_vid);

	MLX5_SET_CFG(in, start_flow_index, ix);

	ix += MLX5E_VLAN_GROUP0_SIZE;
@@ -1003,7 +1003,7 @@ static int __mlx5e_create_vlan_table_groups(struct mlx5e_flow_table *ft, u32 *in 


	memset(in, 0, inlen);

	MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);

	MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.vlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.cvlan_tag);

	MLX5_SET_CFG(in, start_flow_index, ix);

	ix += MLX5E_VLAN_GROUP1_SIZE;

	MLX5_SET_CFG(in, end_flow_index, ix - 1);

drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c

+2 −2
Original line number Diff line number Diff line
@@ -237,9 +237,9 @@ static int set_flow_attrs(u32 *match_c, u32 *match_v, 
	if ((fs->flow_type & FLOW_EXT) &&

	    (fs->m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {

		MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,

			 vlan_tag, 1);

			 cvlan_tag, 1);

		MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,

			 vlan_tag, 1);

			 cvlan_tag, 1);

		MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,

			 first_vid, 0xfff);

		MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,

drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

+2 −2
Original line number Diff line number Diff line
@@ -460,8 +460,8 @@ static int __parse_cls_flower(struct mlx5e_priv *priv, 
						  FLOW_DISSECTOR_KEY_VLAN,

						  f->mask);

		if (mask->vlan_id || mask->vlan_priority) {

			MLX5_SET(fte_match_set_lyr_2_4, headers_c, vlan_tag, 1);

			MLX5_SET(fte_match_set_lyr_2_4, headers_v, vlan_tag, 1);

			MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);

			MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);



			MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);

			MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);

drivers/net/ethernet/mellanox/mlx5/core/eswitch.c

+6 −6
Original line number Diff line number Diff line
@@ -979,7 +979,7 @@ static int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw, 


	MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);

	match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);

	MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.cvlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid);

	MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);

	MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
@@ -1098,7 +1098,7 @@ static int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw, 
	match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);



	MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);

	MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.cvlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);

	MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);

	MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
@@ -1115,7 +1115,7 @@ static int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw, 


	memset(flow_group_in, 0, inlen);

	MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);

	MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.cvlan_tag);

	MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);

	MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
@@ -1254,7 +1254,7 @@ static int esw_vport_ingress_config(struct mlx5_eswitch *esw, 
	}



	if (vport->info.vlan || vport->info.qos)

		MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);

		MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);



	if (vport->info.spoofchk) {

		MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_47_16);
@@ -1335,8 +1335,8 @@ static int esw_vport_egress_config(struct mlx5_eswitch *esw, 
	}



	/* Allowed vlan rule */

	MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.vlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.cvlan_tag);

	MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);

	MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vport->info.vlan);

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