Commit 104a0c02 authored by Andrew Pinski's avatar Andrew Pinski Committed by Catalin Marinas
Browse files

arm64: Add workaround for Cavium erratum 27456 



On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
instructions may cause the icache to become corrupted if it contains
data for a non-current ASID.

This patch implements the workaround (which invalidates the local
icache when switching the mm) by using code patching.

Signed-off-by: default avatarAndrew Pinski <apinski@cavium.com>
Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 2f39b5f9

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -56,3 +56,4 @@ stable kernels. 
|                |                 |                 |                         |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |

| Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |

| Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |

arch/arm64/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -435,6 +435,17 @@ config CAVIUM_ERRATUM_23154 


	  If unsure, say Y.



config CAVIUM_ERRATUM_27456

	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"

	default y

	help

	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI

	  instructions may cause the icache to become corrupted if it

	  contains data for a non-current ASID.  The fix is to

	  invalidate the icache when changing the mm context.



	  If unsure, say Y.



endmenu

arch/arm64/include/asm/cpufeature.h

+2 −1
Original line number Diff line number Diff line
@@ -33,8 +33,9 @@ 
#define ARM64_HAS_NO_HW_PREFETCH		8

#define ARM64_HAS_UAO				9

#define ARM64_ALT_PAN_NOT_UAO			10

#define ARM64_WORKAROUND_CAVIUM_27456		12



#define ARM64_NCAPS				11

#define ARM64_NCAPS				13



#ifndef __ASSEMBLY__

arch/arm64/kernel/cpu_errata.c

+9 −0
Original line number Diff line number Diff line
@@ -87,6 +87,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.capability = ARM64_WORKAROUND_CAVIUM_23154,

		MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),

	},

#endif

#ifdef CONFIG_CAVIUM_ERRATUM_27456

	{

	/* Cavium ThunderX, T88 pass 1.x - 2.1 */

		.desc = "Cavium erratum 27456",

		.capability = ARM64_WORKAROUND_CAVIUM_27456,

		MIDR_RANGE(MIDR_THUNDERX, 0x00,

			   (1 << MIDR_VARIANT_SHIFT) | 1),

	},

#endif

	{

	}

arch/arm64/mm/proc.S

+12 −0
Original line number Diff line number Diff line
@@ -25,6 +25,8 @@ 
#include <asm/hwcap.h>

#include <asm/pgtable-hwdef.h>

#include <asm/pgtable.h>

#include <asm/cpufeature.h>

#include <asm/alternative.h>



#include "proc-macros.S"
@@ -137,7 +139,17 @@ ENTRY(cpu_do_switch_mm) 
	bfi	x0, x1, #48, #16		// set the ASID

	msr	ttbr0_el1, x0			// set TTBR0

	isb

alternative_if_not ARM64_WORKAROUND_CAVIUM_27456

	ret

	nop

	nop

	nop

alternative_else

	ic	iallu

	dsb	nsh

	isb

	ret

alternative_endif

ENDPROC(cpu_do_switch_mm)



	.pushsection ".idmap.text", "ax"

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