Commit 1027247f authored by Russell King's avatar Russell King
Browse files

ARM: Add L2 cache handling to smp boot support 



The page table and secondary data which we're asking the secondary CPU
to make use of has to hit RAM to ensure that the secondary CPU can see
it since it may not be taking part in coherency or cache searches at
this point.

Acked-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent d10fca9f

arch/arm/kernel/smp.c

+3 −1
Original line number Diff line number Diff line
@@ -99,6 +99,7 @@ int __cpuinit __cpu_up(unsigned int cpu) 
	*pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) |

		     PMD_TYPE_SECT | PMD_SECT_AP_WRITE);

	flush_pmd_entry(pmd);

	outer_clean_range(__pa(pmd), __pa(pmd + 1));



	/*

	 * We need to tell the secondary core where to find
@@ -106,7 +107,8 @@ int __cpuinit __cpu_up(unsigned int cpu) 
	 */

	secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;

	secondary_data.pgdir = virt_to_phys(pgd);

	wmb();

	__cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));

	outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));



	/*

	 * Now bring the CPU into our world.

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