Commit 10086b34 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'hns3-next' 



Huazhong Tan says:

====================
net: hns3: add some cleanups & bugfix

This patch-set includes cleanups and bugfix for the HNS3 ethernet
controller driver.

[patch 01/06 - 03/06] adds some cleanups.

[patch 04/06] changes the print level of RAS.

[patch 05/06] fixes a bug related to MAC TNL.

[patch 06/06] adds phy_attached_info().
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents d83d508b 1bef61fc

drivers/net/ethernet/hisilicon/hns3/hnae3.c

+4 −5
Original line number Diff line number Diff line
@@ -104,7 +104,6 @@ int hnae3_register_client(struct hnae3_client *client) 
{

	struct hnae3_client *client_tmp;

	struct hnae3_ae_dev *ae_dev;

	int ret = 0;



	if (!client)

		return -ENODEV;
@@ -123,7 +122,7 @@ int hnae3_register_client(struct hnae3_client *client) 
		/* if the client could not be initialized on current port, for

		 * any error reasons, move on to next available port

		 */

		ret = hnae3_init_client_instance(client, ae_dev);

		int ret = hnae3_init_client_instance(client, ae_dev);

		if (ret)

			dev_err(&ae_dev->pdev->dev,

				"match and instantiation failed for port, ret = %d\n",
@@ -164,7 +163,7 @@ void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo) 
	const struct pci_device_id *id;

	struct hnae3_ae_dev *ae_dev;

	struct hnae3_client *client;

	int ret = 0;

	int ret;



	if (!ae_algo)

		return;
@@ -258,7 +257,7 @@ int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev) 
	const struct pci_device_id *id;

	struct hnae3_ae_algo *ae_algo;

	struct hnae3_client *client;

	int ret = 0;

	int ret;



	if (!ae_dev)

		return -ENODEV;

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+4 −4
Original line number Diff line number Diff line
@@ -229,9 +229,9 @@ static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 
	/* initialize the configuration for interrupt coalescing.

	 * 1. GL (Interrupt Gap Limiter)

	 * 2. RL (Interrupt Rate Limiter)

	 *

	 * Default: enable interrupt coalescing self-adaptive and GL

	 */



	/* Default: enable interrupt coalescing self-adaptive and GL */

	tqp_vector->tx_group.coal.gl_adapt_enable = 1;

	tqp_vector->rx_group.coal.gl_adapt_enable = 1;
@@ -4207,8 +4207,8 @@ int hns3_nic_reset_all_ring(struct hnae3_handle *h) 
static void hns3_store_coal(struct hns3_nic_priv *priv)

{

	/* ethtool only support setting and querying one coal

	 * configuation for now, so save the vector 0' coal

	 * configuation here in order to restore it.

	 * configuration for now, so save the vector 0' coal

	 * configuration here in order to restore it.

	 */

	memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,

	       sizeof(struct hns3_enet_coalesce));

drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c

+3 −3
Original line number Diff line number Diff line
@@ -704,7 +704,7 @@ static int hns3_get_link_ksettings(struct net_device *netdev, 
	return 0;

}



static int hns3_check_ksettings_param(struct net_device *netdev,

static int hns3_check_ksettings_param(const struct net_device *netdev,

				      const struct ethtool_link_ksettings *cmd)

{

	struct hnae3_handle *handle = hns3_get_handle(netdev);
@@ -749,7 +749,7 @@ static int hns3_set_link_ksettings(struct net_device *netdev, 
{

	struct hnae3_handle *handle = hns3_get_handle(netdev);

	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;

	int ret = 0;

	int ret;



	/* Chip don't support this mode. */

	if (cmd->base.speed == SPEED_1000 && cmd->base.duplex == DUPLEX_HALF)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

+3 −0
Original line number Diff line number Diff line
@@ -897,14 +897,17 @@ static void hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, u8 stage, 
	dev_info(&hdev->pdev->dev, " read result tcam key %s(%u):\n",

		 sel_x ? "x" : "y", loc);



	/* tcam_data0 ~ tcam_data1 */

	req = (u32 *)req1->tcam_data;

	for (i = 0; i < 2; i++)

		dev_info(&hdev->pdev->dev, "%08x\n", *req++);



	/* tcam_data2 ~ tcam_data7 */

	req = (u32 *)req2->tcam_data;

	for (i = 0; i < 6; i++)

		dev_info(&hdev->pdev->dev, "%08x\n", *req++);



	/* tcam_data8 ~ tcam_data12 */

	req = (u32 *)req3->tcam_data;

	for (i = 0; i < 5; i++)

		dev_info(&hdev->pdev->dev, "%08x\n", *req++);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

+45 −45
Original line number Diff line number Diff line
@@ -637,7 +637,7 @@ static void hclge_log_error(struct device *dev, char *reg, 
{

	while (err->msg) {

		if (err->int_msk & err_sts) {

			dev_warn(dev, "%s %s found [error status=0x%x]\n",

			dev_err(dev, "%s %s found [error status=0x%x]\n",

				reg, err->msg, err_sts);

			if (err->reset_level &&

			    err->reset_level != HNAE3_NONE_RESET)
@@ -1163,7 +1163,7 @@ static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev, 


	status = le32_to_cpu(*(desc_data + 3)) & BIT(0);

	if (status) {

		dev_warn(dev, "SSU_ECC_MULTI_BIT_INT_1 ssu_mem32_ecc_mbit_err found [error status=0x%x]\n",

		dev_err(dev, "SSU_ECC_MULTI_BIT_INT_1 ssu_mem32_ecc_mbit_err found [error status=0x%x]\n",

			status);

		set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req);

	}
@@ -1200,8 +1200,8 @@ static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev, 
	desc_data = (__le32 *)&desc[5];

	status = le32_to_cpu(*(desc_data + 1));

	if (status) {

		dev_warn(dev, "PPU_MPF_ABNORMAL_INT_ST1 %s found\n",

			 "rpu_rx_pkt_ecc_mbit_err");

		dev_err(dev,

			"PPU_MPF_ABNORMAL_INT_ST1 rpu_rx_pkt_ecc_mbit_err found\n");

		set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req);

	}
@@ -1379,15 +1379,15 @@ static int hclge_log_rocee_axi_error(struct hclge_dev *hdev) 
		return ret;

	}



	dev_info(dev, "AXI1: %08X %08X %08X %08X %08X %08X\n",

	dev_err(dev, "AXI1: %08X %08X %08X %08X %08X %08X\n",

		le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]),

		le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]),

		le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5]));

	dev_info(dev, "AXI2: %08X %08X %08X %08X %08X %08X\n",

	dev_err(dev, "AXI2: %08X %08X %08X %08X %08X %08X\n",

		le32_to_cpu(desc[1].data[0]), le32_to_cpu(desc[1].data[1]),

		le32_to_cpu(desc[1].data[2]), le32_to_cpu(desc[1].data[3]),

		le32_to_cpu(desc[1].data[4]), le32_to_cpu(desc[1].data[5]));

	dev_info(dev, "AXI3: %08X %08X %08X %08X\n",

	dev_err(dev, "AXI3: %08X %08X %08X %08X\n",

		le32_to_cpu(desc[2].data[0]), le32_to_cpu(desc[2].data[1]),

		le32_to_cpu(desc[2].data[2]), le32_to_cpu(desc[2].data[3]));
@@ -1408,11 +1408,11 @@ static int hclge_log_rocee_ecc_error(struct hclge_dev *hdev) 
		return ret;

	}



	dev_info(dev, "ECC1: %08X %08X %08X %08X %08X %08X\n",

	dev_err(dev, "ECC1: %08X %08X %08X %08X %08X %08X\n",

		le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]),

		le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]),

		le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5]));

	dev_info(dev, "ECC2: %08X %08X %08X\n", le32_to_cpu(desc[1].data[0]),

	dev_err(dev, "ECC2: %08X %08X %08X\n", le32_to_cpu(desc[1].data[0]),

		le32_to_cpu(desc[1].data[1]), le32_to_cpu(desc[1].data[2]));



	return 0;
@@ -1442,7 +1442,7 @@ static int hclge_log_rocee_ovf_error(struct hclge_dev *hdev) 
			  le32_to_cpu(desc[0].data[0]);

		while (err->msg) {

			if (err->int_msk == err_sts) {

				dev_warn(dev, "%s [error status=0x%x] found\n",

				dev_err(dev, "%s [error status=0x%x] found\n",

					err->msg,

					le32_to_cpu(desc[0].data[0]));

				break;
@@ -1452,12 +1452,12 @@ static int hclge_log_rocee_ovf_error(struct hclge_dev *hdev) 
	}



	if (le32_to_cpu(desc[0].data[1]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) {

		dev_warn(dev, "ROCEE TSP OVF [error status=0x%x] found\n",

		dev_err(dev, "ROCEE TSP OVF [error status=0x%x] found\n",

			le32_to_cpu(desc[0].data[1]));

	}



	if (le32_to_cpu(desc[0].data[2]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) {

		dev_warn(dev, "ROCEE SCC OVF [error status=0x%x] found\n",

		dev_err(dev, "ROCEE SCC OVF [error status=0x%x] found\n",

			le32_to_cpu(desc[0].data[2]));

	}
@@ -1486,10 +1486,10 @@ hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev) 


	if (status & HCLGE_ROCEE_AXI_ERR_INT_MASK) {

		if (status & HCLGE_ROCEE_RERR_INT_MASK)

			dev_warn(dev, "ROCEE RAS AXI rresp error\n");

			dev_err(dev, "ROCEE RAS AXI rresp error\n");



		if (status & HCLGE_ROCEE_BERR_INT_MASK)

			dev_warn(dev, "ROCEE RAS AXI bresp error\n");

			dev_err(dev, "ROCEE RAS AXI bresp error\n");



		reset_type = HNAE3_FUNC_RESET;
@@ -1499,7 +1499,7 @@ hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev) 
	}



	if (status & HCLGE_ROCEE_ECC_INT_MASK) {

		dev_warn(dev, "ROCEE RAS 2bit ECC error\n");

		dev_err(dev, "ROCEE RAS 2bit ECC error\n");

		reset_type = HNAE3_GLOBAL_RESET;



		ret = hclge_log_rocee_ecc_error(hdev);
@@ -1557,8 +1557,8 @@ int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en) 


static void hclge_handle_rocee_ras_error(struct hnae3_ae_dev *ae_dev)

{

	enum hnae3_reset_type reset_type = HNAE3_NONE_RESET;

	struct hclge_dev *hdev = ae_dev->priv;

	enum hnae3_reset_type reset_type;



	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||

	    hdev->pdev->revision < 0x21)
@@ -1640,7 +1640,7 @@ pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev) 


	/* Handling Non-fatal HNS RAS errors */

	if (status & HCLGE_RAS_REG_NFE_MASK) {

		dev_warn(dev,

		dev_err(dev,

			"HNS Non-Fatal RAS error(status=0x%x) identified\n",

			status);

		hclge_handle_all_ras_errors(hdev);
@@ -1649,7 +1649,7 @@ pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev) 
	/* Handling Non-fatal Rocee RAS errors */

	if (hdev->pdev->revision >= 0x21 &&

	    status & HCLGE_RAS_REG_ROCEE_ERR_MASK) {

		dev_warn(dev, "ROCEE Non-Fatal RAS error identified\n");

		dev_err(dev, "ROCEE Non-Fatal RAS error identified\n");

		hclge_handle_rocee_ras_error(ae_dev);

	}
@@ -1728,7 +1728,7 @@ static void hclge_handle_over_8bd_err(struct hclge_dev *hdev, 
		return;

	}



	dev_warn(dev, "PPU_PF_ABNORMAL_INT_ST over_8bd_no_fe found, vf_id(%d), queue_id(%d)\n",

	dev_err(dev, "PPU_PF_ABNORMAL_INT_ST over_8bd_no_fe found, vf_id(%u), queue_id(%u)\n",

		vf_id, q_id);



	if (vf_id) {
@@ -1746,7 +1746,7 @@ static void hclge_handle_over_8bd_err(struct hclge_dev *hdev, 


		ret = hclge_inform_reset_assert_to_vf(&hdev->vport[vf_id]);

		if (ret)

			dev_warn(dev, "inform reset to vf(%d) failed %d!\n",

			dev_err(dev, "inform reset to vf(%u) failed %d!\n",

				hdev->vport->vport_id, ret);

	} else {

		set_bit(HNAE3_FUNC_RESET, reset_requests);
@@ -1793,7 +1793,7 @@ static int hclge_handle_mpf_msix_error(struct hclge_dev *hdev, 
	status = le32_to_cpu(*(desc_data + 2)) &

			HCLGE_PPU_MPF_INT_ST2_MSIX_MASK;

	if (status)

		dev_warn(dev, "PPU_MPF_ABNORMAL_INT_ST2 rx_q_search_miss found [dfx status=0x%x\n]",

		dev_err(dev, "PPU_MPF_ABNORMAL_INT_ST2 rx_q_search_miss found [dfx status=0x%x\n]",

			status);



	/* clear all main PF MSIx errors */
@@ -1988,7 +1988,7 @@ void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev) 


	/* Handle Non-fatal HNS RAS errors */

	if (status & HCLGE_RAS_REG_NFE_MASK) {

		dev_warn(dev, "HNS hw error(RAS) identified during init\n");

		dev_err(dev, "HNS hw error(RAS) identified during init\n");

		hclge_handle_all_ras_errors(hdev);

	}

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