ARM: dts: socfpga: update NAND clocking for c5/a5 (0ffc5df8) · Commits · 戴 / test

The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). The nand_x_clk and nand_ecc_clk are derived from the nand_clk. The nand_x_clk has a fixed divider of 4. Also, update the NAND dts property with the correct clocks property. Signed-off-by:

Dinh Nguyen <dinguyen@kernel.org> --- v2: add nand_ecc_clk and update commit message

arch/arm/boot/dts/socfpga.dtsi

+10 −2

Original line number	Diff line number	Diff line
		@@ -483,10 +483,17 @@
		clk-gate = <0xa0 9>;
		};

		nand_ecc_clk: nand_ecc_clk {
		#clock-cells = <0>;
		compatible = "altr,socfpga-gate-clk";
		clocks = <&nand_x_clk>;
		clk-gate = <0xa0 9>;
		};

		nand_clk: nand_clk {
		#clock-cells = <0>;
		compatible = "altr,socfpga-gate-clk";
		clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
		clocks = <&nand_x_clk>;
		clk-gate = <0xa0 10>;
		fixed-divider = <4>;
		};
		@@ -754,7 +761,8 @@
		reg-names = "nand_data", "denali_reg";
		interrupts = <0x0 0x90 0x4>;
		dma-mask = <0xffffffff>;
		clocks = <&nand_x_clk>;
		clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
		clock-names = "nand", "nand_x", "ecc";
		status = "disabled";
		};

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