Commit 0ff5a481 authored by Dinh Nguyen's avatar Dinh Nguyen
Browse files

ARM: dts: socfpga: fix register entry for timer3 on Arria10 



Fixes the register address for the timer3 entry on Arria10.

Fixes: 475dc86d ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 9123e3a7

arch/arm/boot/dts/socfpga_arria10.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -821,7 +821,7 @@ 
		timer3: timer3@ffd00100 {

			compatible = "snps,dw-apb-timer";

			interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0xffd01000 0x100>;

			reg = <0xffd00100 0x100>;

			clocks = <&l4_sys_free_clk>;

			clock-names = "timer";

			resets = <&rst L4SYSTIMER1_RESET>;

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