Commit 0f9aeeac authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2018-09-14' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "This is the general drm fixes pull for rc4.

  i915:
   - Two GVT fixes (one for the mm reference issue you pointed out)
   - Gen 2 video playback fix
   - IPS timeout error suppression on Broadwell

  amdgpu:
   - Small memory leak
   - SR-IOV reset
   - locking fix
   - updated SDMA golden registers

  nouveau:
   - Remove some leftover debugging"

* tag 'drm-fixes-2018-09-14' of git://anongit.freedesktop.org/drm/drm:
  drm/nouveau/devinit: fix warning when PMU/PRE_OS is missing
  drm/amdgpu: fix error handling in amdgpu_cs_user_fence_chunk
  drm/i915/overlay: Allocate physical registers from stolen
  drm/amdgpu: move PSP init prior to IH in gpu reset
  drm/amdgpu: Fix SDMA hang in prt mode v2
  drm/amdgpu: fix amdgpu_mn_unlock() in the CS error path
  drm/i915/bdw: Increase IPS disable timeout to 100ms
  drm/i915/gvt: Fix the incorrect length of child_device_config issue
  drm/i915/gvt: Fix life cycle reference on KVM mm
parents 145ea6f1 2b6318a0

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+16 −9
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, 
{

	struct drm_gem_object *gobj;

	unsigned long size;

	int r;



	gobj = drm_gem_object_lookup(p->filp, data->handle);

	if (gobj == NULL)
@@ -50,20 +51,26 @@ static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, 
	p->uf_entry.tv.shared = true;

	p->uf_entry.user_pages = NULL;



	size = amdgpu_bo_size(p->uf_entry.robj);

	if (size != PAGE_SIZE || (data->offset + 8) > size)

		return -EINVAL;



	*offset = data->offset;



	drm_gem_object_put_unlocked(gobj);



	size = amdgpu_bo_size(p->uf_entry.robj);

	if (size != PAGE_SIZE || (data->offset + 8) > size) {

		r = -EINVAL;

		goto error_unref;

	}



	if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {

		amdgpu_bo_unref(&p->uf_entry.robj);

		return -EINVAL;

		r = -EINVAL;

		goto error_unref;

	}



	*offset = data->offset;



	return 0;



error_unref:

	amdgpu_bo_unref(&p->uf_entry.robj);

	return r;

}



static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
@@ -1262,10 +1269,10 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 
error_abort:

	dma_fence_put(&job->base.s_fence->finished);

	job->base.s_fence = NULL;

	amdgpu_mn_unlock(p->mn);



error_unlock:

	amdgpu_job_free(job);

	amdgpu_mn_unlock(p->mn);

	return r;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -2063,6 +2063,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) 
	static enum amd_ip_block_type ip_order[] = {

		AMD_IP_BLOCK_TYPE_GMC,

		AMD_IP_BLOCK_TYPE_COMMON,

		AMD_IP_BLOCK_TYPE_PSP,

		AMD_IP_BLOCK_TYPE_IH,

	};
@@ -2093,7 +2094,6 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) 


	static enum amd_ip_block_type ip_order[] = {

		AMD_IP_BLOCK_TYPE_SMC,

		AMD_IP_BLOCK_TYPE_PSP,

		AMD_IP_BLOCK_TYPE_DCE,

		AMD_IP_BLOCK_TYPE_GFX,

		AMD_IP_BLOCK_TYPE_SDMA,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+5 −2
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = { 
	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
@@ -81,7 +82,8 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = { 
	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0)

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)

};



static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
@@ -109,7 +111,8 @@ static const struct soc15_reg_golden golden_settings_sdma_4_1[] = 
	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0)

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)

};



static const struct soc15_reg_golden golden_settings_sdma_4_2[] =

drivers/gpu/drm/i915/gvt/kvmgt.c

+8 −2
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#include <linux/device.h>

#include <linux/mm.h>

#include <linux/mmu_context.h>

#include <linux/sched/mm.h>

#include <linux/types.h>

#include <linux/list.h>

#include <linux/rbtree.h>
@@ -1792,16 +1793,21 @@ static int kvmgt_rw_gpa(unsigned long handle, unsigned long gpa, 
	info = (struct kvmgt_guest_info *)handle;

	kvm = info->kvm;



	if (kthread)

	if (kthread) {

		if (!mmget_not_zero(kvm->mm))

			return -EFAULT;

		use_mm(kvm->mm);

	}



	idx = srcu_read_lock(&kvm->srcu);

	ret = write ? kvm_write_guest(kvm, gpa, buf, len) :

		      kvm_read_guest(kvm, gpa, buf, len);

	srcu_read_unlock(&kvm->srcu, idx);



	if (kthread)

	if (kthread) {

		unuse_mm(kvm->mm);

		mmput(kvm->mm);

	}



	return ret;

}

drivers/gpu/drm/i915/gvt/opregion.c

+9 −11
Original line number Diff line number Diff line
@@ -42,8 +42,6 @@ 
#define DEVICE_TYPE_EFP3   0x20

#define DEVICE_TYPE_EFP4   0x10



#define DEV_SIZE	38



struct opregion_header {

	u8 signature[16];

	u32 size;
@@ -63,6 +61,10 @@ struct bdb_data_header { 
	u16 size; /* data size */

} __packed;



/* For supporting windows guest with opregion, here hardcode the emulated

 * bdb header version as '186', and the corresponding child_device_config

 * length should be '33' but not '38'.

 */

struct efp_child_device_config {

	u16 handle;

	u16 device_type;
@@ -109,12 +111,6 @@ struct efp_child_device_config { 
	u8 mipi_bridge_type; /* 171 */

	u16 device_class_ext;

	u8 dvo_function;

	u8 dp_usb_type_c:1; /* 195 */

	u8 skip6:7;

	u8 dp_usb_type_c_2x_gpio_index; /* 195 */

	u16 dp_usb_type_c_2x_gpio_pin; /* 195 */

	u8 iboost_dp:4; /* 196 */

	u8 iboost_hdmi:4; /* 196 */

} __packed;



struct vbt {
@@ -155,7 +151,7 @@ static void virt_vbt_generation(struct vbt *v) 
	v->header.bdb_offset = offsetof(struct vbt, bdb_header);



	strcpy(&v->bdb_header.signature[0], "BIOS_DATA_BLOCK");

	v->bdb_header.version = 186; /* child_dev_size = 38 */

	v->bdb_header.version = 186; /* child_dev_size = 33 */

	v->bdb_header.header_size = sizeof(v->bdb_header);



	v->bdb_header.bdb_size = sizeof(struct vbt) - sizeof(struct vbt_header)
@@ -169,11 +165,13 @@ static void virt_vbt_generation(struct vbt *v) 


	/* child device */

	num_child = 4; /* each port has one child */

	v->general_definitions.child_dev_size =

		sizeof(struct efp_child_device_config);

	v->general_definitions_header.id = BDB_GENERAL_DEFINITIONS;

	/* size will include child devices */

	v->general_definitions_header.size =

		sizeof(struct bdb_general_definitions) + num_child * DEV_SIZE;

	v->general_definitions.child_dev_size = DEV_SIZE;

		sizeof(struct bdb_general_definitions) +

			num_child * v->general_definitions.child_dev_size;



	/* portA */

	v->child0.handle = DEVICE_TYPE_EFP1;

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