Commit 0f7be8f5 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'sunxi-dt-for-5.1' of... 

Merge tag 'sunxi-dt-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Allwinner DT changes for 5.1

As usual, this is a random assortment of changes:

  - ARM PMU is enabled on the A10
  - The first usage of the PIO pinbank regulator supplies added,
    for the Bananapi
  - Broadcom-based Bluetooth enabled on the Bananapi M2 Magic and M2
    Ultra, using the serdev bindings
  - Video codec added for the A10
  - Display pipeline for the A23 added and enabled for the generic Q8
    tablets

* tag 'sunxi-dt-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux

:
  ARM: dts: sun8i-a23-q8: Set compatible string for LCD panel
  ARM: dts: sun8i-q8-common: Enable display pipeline with RGB LCD panel
  ARM: dts: sun8i-a23: Add compatible strings to display pipeline device nodes
  ARM: dts: sun8i-a33: Move display pipeline nodes to a23/a33 common dtsi
  ARM: dts: sun8i-a23-a33: Move NAND controller device node to sort by address
  ARM: dts: sun4i-a10: Add Video Engine and reserved memory nodes
  ARM: dts: sun4i: Add support for the C1 SRAM region with the SRAM controller
  ARM: dts: sunxi: bananapi-m2-plus: Add Bluetooth device node
  ARM: dts: sun8i: r40: bananapi-m2-ultra: Add Bluetooth device node
  ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix WiFi regulator definitions
  ARM: dts: sun8i: r40: Add pinmux setting for CLK_OUT_A
  ARM: dts: sun8i: r40: Add pinmux settings for UART3 on PG pingroup
  ARM: dts: sun7i: bananapi: Add GPIO banks regulators
  ARM: dts: sun4i-a10: Add PMU node

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents d2849a58 55533921

arch/arm/boot/dts/sun4i-a10.dtsi

+44 −0
Original line number Diff line number Diff line
@@ -184,6 +184,26 @@ 
		status = "disabled";

	};



	pmu {

		compatible = "arm,cortex-a8-pmu";

		interrupts = <3>;

	};



	reserved-memory {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */

		default-pool {

			compatible = "shared-dma-pool";

			size = <0x6000000>;

			alloc-ranges = <0x4a000000 0x6000000>;

			reusable;

			linux,cma-default;

		};

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <1>;
@@ -224,6 +244,19 @@ 
					status = "disabled";

				};

			};



			sram_c: sram@1d00000 {

				compatible = "mmio-sram";

				reg = <0x01d00000 0xd0000>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x01d00000 0xd0000>;



				ve_sram: sram-section@0 {

					compatible = "allwinner,sun4i-a10-sram-c1";

					reg = <0x000000 0x80000>;

				};

			};

		};



		dma: dma-controller@1c02000 {
@@ -394,6 +427,17 @@ 
			};

		};



		video-codec@1c0e000 {

			compatible = "allwinner,sun4i-a10-video-engine";

			reg = <0x01c0e000 0x1000>;

			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,

				 <&ccu CLK_DRAM_VE>;

			clock-names = "ahb", "mod", "ram";

			resets = <&ccu RST_VE>;

			interrupts = <53>;

			allwinner,sram = <&ve_sram 1>;

		};



		mmc0: mmc@1c0f000 {

			compatible = "allwinner,sun4i-a10-mmc";

			reg = <0x01c0f000 0x1000>;

arch/arm/boot/dts/sun7i-a20-bananapi.dts

+5 −0
Original line number Diff line number Diff line
@@ -191,6 +191,11 @@ 
};



&pio {

	vcc-pa-supply = <&reg_vcc3v3>;

	vcc-pc-supply = <&reg_vcc3v3>;

	vcc-pe-supply = <&reg_vcc3v3>;

	vcc-pf-supply = <&reg_vcc3v3>;

	vcc-pg-supply = <&reg_vcc3v3>;

	gpio-line-names =

		/* PA */

		"ERXD3", "ERXD2", "ERXD1", "ERXD0", "ETXD3",

arch/arm/boot/dts/sun8i-a23-a33.dtsi

+160 −15
Original line number Diff line number Diff line
@@ -68,6 +68,12 @@ 
		};

	};



	de: display-engine {

		/* compatible gets set in SoC specific dtsi file */

		allwinner,pipelines = <&fe0>;

		status = "disabled";

	};



	timer {

		compatible = "arm,armv7-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -155,6 +161,55 @@ 
			#dma-cells = <1>;

		};



		nfc: nand@1c03000 {

			compatible = "allwinner,sun4i-a10-nand";

			reg = <0x01c03000 0x1000>;

			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;

			clock-names = "ahb", "mod";

			resets = <&ccu RST_BUS_NAND>;

			reset-names = "ahb";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		tcon0: lcd-controller@1c0c000 {

			/* compatible gets set in SoC specific dtsi file */

			reg = <0x01c0c000 0x1000>;

			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_LCD>,

				 <&ccu CLK_LCD_CH0>;

			clock-names = "ahb",

				      "tcon-ch0";

			clock-output-names = "tcon-pixel-clock";

			resets = <&ccu RST_BUS_LCD>;

			reset-names = "lcd";

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				tcon0_in: port@0 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <0>;



					tcon0_in_drc0: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&drc0_out_tcon0>;

					};

				};



				tcon0_out: port@1 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <1>;

				};

			};

		};



		mmc0: mmc@1c0f000 {

			compatible = "allwinner,sun7i-a20-mmc";

			reg = <0x01c0f000 0x1000>;
@@ -214,21 +269,6 @@ 
			#size-cells = <0>;

		};



		nfc: nand@1c03000 {

			compatible = "allwinner,sun4i-a10-nand";

			reg = <0x01c03000 0x1000>;

			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;

			clock-names = "ahb", "mod";

			resets = <&ccu RST_BUS_NAND>;

			reset-names = "ahb";

			pinctrl-names = "default";

			pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		usb_otg: usb@1c19000 {

			/* compatible gets set in SoC specific dtsi file */

			reg = <0x01c19000 0x0400>;
@@ -572,6 +612,111 @@ 
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

		};



		fe0: display-frontend@1e00000 {

			/* compatible gets set in SoC specific dtsi file */

			reg = <0x01e00000 0x20000>;

			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,

				 <&ccu CLK_DRAM_DE_FE>;

			clock-names = "ahb", "mod",

				      "ram";

			resets = <&ccu RST_BUS_DE_FE>;



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				fe0_out: port@1 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <1>;



					fe0_out_be0: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&be0_in_fe0>;

					};

				};

			};

		};



		be0: display-backend@1e60000 {

			/* compatible gets set in SoC specific dtsi file */

			reg = <0x01e60000 0x10000>;

			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,

				 <&ccu CLK_DRAM_DE_BE>;

			clock-names = "ahb", "mod",

				      "ram";

			resets = <&ccu RST_BUS_DE_BE>;



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				be0_in: port@0 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <0>;



					be0_in_fe0: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&fe0_out_be0>;

					};

				};



				be0_out: port@1 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <1>;



					be0_out_drc0: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&drc0_in_be0>;

					};

				};

			};

		};



		drc0: drc@1e70000 {

			/* compatible gets set in SoC specific dtsi file */

			reg = <0x01e70000 0x10000>;

			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,

				 <&ccu CLK_DRAM_DRC>;

			clock-names = "ahb", "mod", "ram";

			resets = <&ccu RST_BUS_DRC>;



			assigned-clocks = <&ccu CLK_DRC>;

			assigned-clock-rates = <300000000>;



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				drc0_in: port@0 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <0>;



					drc0_in_be0: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&be0_out_drc0>;

					};

				};



				drc0_out: port@1 {

					#address-cells = <1>;

					#size-cells = <0>;

					reg = <1>;



					drc0_out_tcon0: endpoint@0 {

						reg = <0>;

						remote-endpoint = <&tcon0_in_drc0>;

					};

				};

			};

		};



		rtc: rtc@1f00000 {

			compatible = "allwinner,sun8i-a23-rtc";

			reg = <0x01f00000 0x400>;

arch/arm/boot/dts/sun8i-a23-q8-tablet.dts

+4 −0
Original line number Diff line number Diff line
@@ -61,3 +61,7 @@ 
		"Headset Mic", "HBIAS";

	status = "okay";

};



&panel {

	compatible = "bananapi,s070wv20-ct16", "simple-panel";

};

arch/arm/boot/dts/sun8i-a23.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -62,10 +62,26 @@ 
	};

};



&be0 {

	compatible = "allwinner,sun8i-a23-display-backend";

};



&ccu {

	compatible = "allwinner,sun8i-a23-ccu";

};



&de {

	compatible = "allwinner,sun8i-a23-display-engine";

};



&drc0 {

	compatible = "allwinner,sun8i-a23-drc";

};



&fe0 {

	compatible = "allwinner,sun8i-a23-display-frontend";

};



&pio {

	compatible = "allwinner,sun8i-a23-pinctrl";

	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
@@ -73,6 +89,10 @@ 
		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

};



&tcon0 {

	compatible = "allwinner,sun8i-a23-tcon";

};



&usb_otg {

	compatible = "allwinner,sun6i-a31-musb";

};

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