KVM: MIPS: Enable KVM support for Loongson-3 (0f78355c) · Commits · 戴 / test

This patch enable KVM support for Loongson-3 by selecting HAVE_KVM, but only enable KVM/VZ on Loongson-3A R4+ (because VZ of early processors are incomplete). Besides, Loongson-3 support SMP guests, so we clear the linked load bit of LLAddr in kvm_vz_vcpu_load() if the guest has more than one VCPUs. Acked-by:

Thomas Bogendoerfer <tsbogend@alpha.franken.de> Reviewed-by:

Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by:

Huacai Chen <chenhc@lemote.com> Co-developed-by:

Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <1590220602-3547-15-git-send-email-chenhc@lemote.com> Signed-off-by:

Paolo Bonzini <pbonzini@redhat.com>

arch/mips/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -1404,6 +1404,7 @@ config CPU_LOONGSON64
		select MIPS_L1_CACHE_SHIFT_6
		select GPIOLIB
		select SWIOTLB
		select HAVE_KVM
		help
		The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
		cores implements the MIPS64R2 instruction set with many extensions,

arch/mips/kernel/cpu-probe.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -2076,6 +2076,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
		c->ases \|= (MIPS_ASE_LOONGSON_MMI \| MIPS_ASE_LOONGSON_CAM \|
		MIPS_ASE_LOONGSON_EXT \| MIPS_ASE_LOONGSON_EXT2);
		c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
		break;
		case PRID_IMP_LOONGSON_64G:
		c->cputype = CPU_LOONGSON64;

arch/mips/kvm/vz.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -2697,7 +2697,7 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
		* prevents a SC on the next VCPU from succeeding by matching a LL on
		* the previous VCPU.
		*/
		if (cpu_guest_has_rw_llb)
		if (vcpu->kvm->created_vcpus > 1)
		write_gc0_lladdr(0);

		return 0;

Admin message