Commit 0f71c60f authored by Rob Herring's avatar Rob Herring Committed by Lorenzo Pieralisi
Browse files

PCI: dwc: Remove storing of PCI resources 

The PCI bridge resources are stored in pci_host_bridge.windows, so
there's no need to store them in a DWC specific struct. There's also no
need to parse the resources and store them a 2nd time as they are mainly
used for one time setup of iATU windows.

Link: https://lore.kernel.org/r/20200821035420.380495-19-robh@kernel.org


Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jonathan Chocron <jonnyc@amazon.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
parent 5808d43e

drivers/pci/controller/dwc/pci-keystone.c

+6 −2
Original line number Diff line number Diff line
@@ -400,10 +400,14 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 
	u32 num_viewport = ks_pcie->num_viewport;

	struct dw_pcie *pci = ks_pcie->pci;

	struct pcie_port *pp = &pci->pp;

	u64 start = pp->mem->start;

	u64 end = pp->mem->end;

	u64 start, end;

	struct resource *mem;

	int i;



	mem = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM)->res;

	start = mem->start;

	end = mem->end;



	/* Disable BARs for inbound access */

	ks_pcie_set_dbi_mode(ks_pcie);

	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);

drivers/pci/controller/dwc/pcie-al.c

+4 −3
Original line number Diff line number Diff line
@@ -260,6 +260,7 @@ static void al_pcie_config_prepare(struct al_pcie *pcie) 
	u8 secondary_bus;

	u32 cfg_control;

	u32 reg;

	struct resource *bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res;



	target_bus_cfg = &pcie->target_bus_cfg;
@@ -273,13 +274,13 @@ static void al_pcie_config_prepare(struct al_pcie *pcie) 
	target_bus_cfg->ecam_mask = ecam_bus_mask;

	/* This portion is taken from the cfg_target_bus reg */

	target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;

	target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg->reg_mask;

	target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask;



	al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,

			       target_bus_cfg->reg_mask);



	secondary_bus = pp->busn->start + 1;

	subordinate_bus = pp->busn->end;

	secondary_bus = bus->start + 1;

	subordinate_bus = bus->end;



	/* Set the valid values of secondary and subordinate buses */

	cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +

drivers/pci/controller/dwc/pcie-designware-host.c

+9 −18
Original line number Diff line number Diff line
@@ -326,17 +326,9 @@ int dw_pcie_host_init(struct pcie_port *pp) 
	resource_list_for_each_entry(win, &bridge->windows) {

		switch (resource_type(win->res)) {

		case IORESOURCE_IO:

			pp->io = win->res;

			pp->io->name = "I/O";

			pp->io_size = resource_size(pp->io);

			pp->io_bus_addr = pp->io->start - win->offset;

			pp->io_base = pci_pio_to_address(pp->io->start);

			break;

		case IORESOURCE_MEM:

			pp->mem = win->res;

			pp->mem->name = "MEM";

			pp->mem_size = resource_size(pp->mem);

			pp->mem_bus_addr = pp->mem->start - win->offset;

			pp->io_size = resource_size(win->res);

			pp->io_bus_addr = win->res->start - win->offset;

			pp->io_base = pci_pio_to_address(win->res->start);

			break;

		case 0:

			pp->cfg = win->res;
@@ -345,9 +337,6 @@ int dw_pcie_host_init(struct pcie_port *pp) 
			pp->cfg0_base = pp->cfg->start;

			pp->cfg1_base = pp->cfg->start + pp->cfg0_size;

			break;

		case IORESOURCE_BUS:

			pp->busn = win->res;

			break;

		}

	}
@@ -361,8 +350,6 @@ int dw_pcie_host_init(struct pcie_port *pp) 
		}

	}



	pp->mem_base = pp->mem->start;



	if (!pp->va_cfg0_base) {

		pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,

					pp->cfg0_base, pp->cfg0_size);
@@ -602,9 +589,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) 
	 * ATU, so we should not program the ATU here.

	 */

	if (pp->bridge->child_ops == &dw_child_pcie_ops) {

		struct resource_entry *entry =

			resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);



		dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,

					  PCIE_ATU_TYPE_MEM, pp->mem_base,

					  pp->mem_bus_addr, pp->mem_size);

					  PCIE_ATU_TYPE_MEM, entry->res->start,

					  entry->res->start - entry->offset,

					  resource_size(entry->res));

		if (pci->num_viewport > 2)

			dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,

						  PCIE_ATU_TYPE_IO, pp->io_base,

drivers/pci/controller/dwc/pcie-designware.h

+0 −6
Original line number Diff line number Diff line
@@ -175,13 +175,7 @@ struct pcie_port { 
	resource_size_t		io_base;

	phys_addr_t		io_bus_addr;

	u32			io_size;

	u64			mem_base;

	phys_addr_t		mem_bus_addr;

	u32			mem_size;

	struct resource		*cfg;

	struct resource		*io;

	struct resource		*mem;

	struct resource		*busn;

	int			irq;

	const struct dw_pcie_host_ops *ops;

	int			msi_irq;

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