ARM: dts: imx7d: add fec1 and fec2 support for i.MX7d soc

				bus-width = <4>;

				status = "disabled";

			};

			fec1: ethernet@30be0000 {

				compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";

				reg = <0x30be0000 0x10000>;

				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,

					<&clks IMX7D_ENET_AXI_ROOT_CLK>,

					<&clks IMX7D_ENET1_TIME_ROOT_CLK>,

					<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,

					<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;

				clock-names = "ipg", "ahb", "ptp",

					"enet_clk_ref", "enet_out";

				fsl,num-tx-queues=<3>;

				fsl,num-rx-queues=<3>;

				status = "disabled";

			};

			fec2: ethernet@30bf0000 {

				compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";

				reg = <0x30bf0000 0x10000>;

				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,

					<&clks IMX7D_ENET_AXI_ROOT_CLK>,

					<&clks IMX7D_ENET2_TIME_ROOT_CLK>,

					<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,

					<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;

				clock-names = "ipg", "ahb", "ptp",

					"enet_clk_ref", "enet_out";

				fsl,num-tx-queues=<3>;

				fsl,num-rx-queues=<3>;

				status = "disabled";

			};

		};

	};

};