Commit 0f2a1484 authored Feb 03, 2016 by Markos Chandras Committed by Ralf Baechle May 13, 2016

MIPS: pm-cps: Avoid offset overflow on MIPSr6



This is similar to commit 934c7923 ("MIPS: asm: r4kcache: Add MIPS
R6 cache unroll functions"). The CACHE instruction has been redefined
for MIPSr6 and it reduced its offset field to 8 bits. This leads to
micro-assembler field overflow warnings when booting SMP MIPSr6 cores
like the following one:

Call Trace:
[<ffffffff8010af88>] show_stack+0x68/0x88
[<ffffffff8056ddf0>] dump_stack+0x68/0x88
[<ffffffff801305bc>] warn_slowpath_common+0x8c/0xc8
[<ffffffff80130630>] warn_slowpath_fmt+0x38/0x48
[<ffffffff80125814>] build_insn+0x514/0x5c0
[<ffffffff806ee134>] cps_gen_cache_routine.isra.3+0xe0/0x1b8
[<ffffffff806ee570>] cps_pm_init+0x364/0x9ec
[<ffffffff80100538>] do_one_initcall+0x90/0x1a8
[<ffffffff806e8c14>] kernel_init_freeable+0x160/0x21c
[<ffffffff8056b6a0>] kernel_init+0x10/0xf8
[<ffffffff801059f8>] ret_from_kernel_thread+0x14/0x1c

We fix this by incrementing the base register on every loop.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12329/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 04d83f94

arch/mips/kernel/pm-cps.c

+11 −4

Original line number	Diff line number	Diff line
		@@ -224,9 +224,16 @@ static void __init cps_gen_cache_routine(u32 pp, struct uasm_label pl,
		uasm_build_label(pl, *pp, lbl);

		/* Generate the cache ops */
		for (i = 0; i < unroll_lines; i++)
		for (i = 0; i < unroll_lines; i++) {
		if (cpu_has_mips_r6) {
		uasm_i_cache(pp, op, 0, t0);
		uasm_i_addiu(pp, t0, t0, cache->linesz);
		} else {
		uasm_i_cache(pp, op, i * cache->linesz, t0);
		}
		}

		if (!cpu_has_mips_r6)
		/* Update the base address */
		uasm_i_addiu(pp, t0, t0, unroll_lines * cache->linesz);

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