Commit 0f1e2f89 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-fixes' into clk-next 

* clk-fixes:
  clk: imx: fix integer overflow in AV PLL round rate
  clk: xgene: Don't call __pa on ioremaped address
  clk: rockchip: don't return NULL when failing to register ddrclk branch
parents a064a07f c7129375

drivers/clk/clk-xgene.c

+4 −6
Original line number Diff line number Diff line
@@ -463,22 +463,20 @@ static int xgene_clk_enable(struct clk_hw *hw) 
	struct xgene_clk *pclk = to_xgene_clk(hw);

	unsigned long flags = 0;

	u32 data;

	phys_addr_t reg;



	if (pclk->lock)

		spin_lock_irqsave(pclk->lock, flags);



	if (pclk->param.csr_reg != NULL) {

		pr_debug("%s clock enabled\n", clk_hw_get_name(hw));

		reg = __pa(pclk->param.csr_reg);

		/* First enable the clock */

		data = xgene_clk_read(pclk->param.csr_reg +

					pclk->param.reg_clk_offset);

		data |= pclk->param.reg_clk_mask;

		xgene_clk_write(data, pclk->param.csr_reg +

					pclk->param.reg_clk_offset);

		pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",

			clk_hw_get_name(hw), &reg,

		pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n",

			clk_hw_get_name(hw),

			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,

			data);
@@ -488,8 +486,8 @@ static int xgene_clk_enable(struct clk_hw *hw) 
		data &= ~pclk->param.reg_csr_mask;

		xgene_clk_write(data, pclk->param.csr_reg +

					pclk->param.reg_csr_offset);

		pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",

			clk_hw_get_name(hw), &reg,

		pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n",

			clk_hw_get_name(hw),

			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,

			data);

	}

drivers/clk/imx/clk-pllv3.c

+6 −2
Original line number Diff line number Diff line
@@ -223,7 +223,7 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, 
	temp64 *= mfn;

	do_div(temp64, mfd);



	return (parent_rate * div) + (u32)temp64;

	return parent_rate * div + (unsigned long)temp64;

}



static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -247,7 +247,11 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, 
	do_div(temp64, parent_rate);

	mfn = temp64;



	return parent_rate * div + parent_rate * mfn / mfd;

	temp64 = (u64)parent_rate;

	temp64 *= mfn;

	do_div(temp64, mfd);



	return parent_rate * div + (unsigned long)temp64;

}



static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/rockchip/clk-ddr.c

+1 −4
Original line number Diff line number Diff line
@@ -144,11 +144,8 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, 
	ddrclk->ddr_flag = ddr_flag;



	clk = clk_register(NULL, &ddrclk->hw);

	if (IS_ERR(clk)) {

		pr_err("%s: could not register ddrclk %s\n", __func__,	name);

	if (IS_ERR(clk))

		kfree(ddrclk);

		return NULL;

	}



	return clk;

}

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