Commit 0efacbba authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC updates from Vineet Gupta:
 "We have a relatively big changeset for ARC for 4.7.

  The highlight is support for EZChip (now Mellanox) NPS-400 network
  processor, a 400-Gb throughput C-programmable packet processor based
  on ARC700 cores from Synopsys. See

        http://www.mellanox.com/related-docs/prod_npu/PB_NPS-400.pdf

  Also present are irqchip and clocksource drivers for NPS as agreed
  with respective maintainers to go via ARC tree due to an soc header
  dependency.  I have the needed ACKs from Jason, Marc, Daniel.  You
  might run into a trivial merge conflict in drivers/irqchip/*

  This EZChip platform support required some deep changes in ARC
  architecture code and also opportunity to cleanup past sins (legacy
  irq domains, missing irq domain lookup, hard coded timer irqs...)

  Summary:

   - Support for EZChip (now Mellanox) NPS-400 Network processor based
     on ARC700

   - NPS interrupt controller and clocksource drivers

   - ARC timers probed off DT

   - ARC iqrchips switching to linear domain (upgrade from legacy
     domains)"

* tag 'arc-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (37 commits)
  arc: axs103_smp: Fix CPU frequency to 100MHz for dual-core
  arc: axs10x: Add DT bindings for I2S PLL Clock
  ARC: pae: STRICT_MM_TYPECHECKS was broken
  ARC: Add eznps platform to Kconfig and Makefile
  ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE
  ARC: [plat-eznps] Use dedicated cpu_relax()
  ARC: [plat-eznps] Use dedicated identity auxiliary register.
  ARC: [plat-eznps] Use dedicated SMP barriers
  ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg
  ARC: [plat-eznps] Use dedicated user stack top
  ARC: [plat-eznps] Add eznps platform
  ARC: [plat-eznps] Add eznps board defconfig and dts
  ARC: Mark secondary cpu online only after all HW setup is done
  ARC: rwlock: disable interrupts in !LLSC variant
  ARC: Make vmalloc size configurable
  ARC: clean out UAPI byteorder.h clean off Kconfig symbol
  irqchip: add nps Internal and external irqchips
  clocksource: Add NPS400 timers driver
  soc: Support for EZchip SoC
  Documentation: Add EZchip vendor to binding list
  ...
parents f4f27d00 776d7f16

Documentation/devicetree/bindings/arc/eznps.txt

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EZchip NPS Network Processor Platforms Device Tree Bindings

---------------------------------------------------------------------------



Appliance main board with NPS400 ASIC.



Required root node properties:

    - compatible = "ezchip,arc-nps";

Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt

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EZchip NPS Interrupt Controller



Required properties:



- compatible : should be "ezchip,nps400-ic"

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.





Example:



intc: interrupt-controller {

	compatible = "ezchip,nps400-ic";

	interrupt-controller;

	#interrupt-cells = <1>;

};

Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt

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NPS Network Processor



Required properties:



- compatible :	should be "ezchip,nps400-timer"



Clocks required for compatible = "ezchip,nps400-timer":

- clocks : Must contain a single entry describing the clock input



Example:



timer {

	compatible = "ezchip,nps400-timer";

	clocks = <&sysclk>;

};

Documentation/devicetree/bindings/timer/snps,arc-timer.txt

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Synopsys ARC Local Timer with Interrupt Capabilities

- Found on all ARC CPUs (ARC700/ARCHS)

- Can be optionally programmed to interrupt on Limit

- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically

  TIMER0 used as clockevent provider (true for all ARC cores)

  TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)



Required properties:



- compatible : should be "snps,arc-timer"

- interrupts : single Interrupt going into parent intc

	       (16 for ARCHS cores, 3 for ARC700 cores)

- clocks     : phandle to the source clock



Optional properties:



- interrupt-parent : phandle to parent intc



Example:



	timer0 {

		compatible = "snps,arc-timer";

		interrupts = <3>;

		interrupt-parent = <&core_intc>;

		clocks = <&core_clk>;

	};



	timer1 {

		compatible = "snps,arc-timer";

		clocks = <&core_clk>;

	};

Documentation/devicetree/bindings/timer/snps,archs-gfrc.txt

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Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs

- clocksource provider for SMP SoC



Required properties:



- compatible : should be "snps,archs-gfrc"

- clocks     : phandle to the source clock



Example:



	gfrc {

		compatible = "snps,archs-gfrc";

		clocks = <&core_clk>;

	};

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