clocksource/drivers/tegra: Cycles can't be 0 (0ef6b01d) · Commits · 戴 / test

Tegra's timer uses n+1 scheme for the counter, i.e. timer will fire after one tick if 0 is loaded. The minimum and maximum numbers of oneshot ticks are defined by clockevents_config_and_register(min, max) invocation and the min value is set to 1 tick. Hence "cycles" value can't ever be 0, unless it's a bug in clocksource core. Signed-off-by:

Dmitry Osipenko <digetx@gmail.com> Acked-by:

Jon Hunter <jonathanh@nvidia.com> Acked-by:

Thierry Reding <treding@nvidia.com> Signed-off-by:

Daniel Lezcano <daniel.lezcano@linaro.org>

drivers/clocksource/timer-tegra.c

+10 −3

Original line number	Diff line number	Diff line
		@@ -56,9 +56,16 @@ static int tegra_timer_set_next_event(unsigned long cycles,
		{
		void __iomem *reg_base = timer_of_base(to_timer_of(evt));

		writel_relaxed(TIMER_PTV_EN \|
		((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */
		reg_base + TIMER_PTV);
		/*
		* Tegra's timer uses n+1 scheme for the counter, i.e. timer will
		* fire after one tick if 0 is loaded.
		*
		* The minimum and maximum numbers of oneshot ticks are defined
		* by clockevents_config_and_register(1, 0x1fffffff + 1) invocation
		* below in the code. Hence the cycles (ticks) can't be outside of
		* a range supportable by hardware.
		*/
		writel_relaxed(TIMER_PTV_EN \| (cycles - 1), reg_base + TIMER_PTV);

		return 0;
		}

Admin message