Commit 0ecee767 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'ux500-dts-arm-soc' of... 

Merge tag 'ux500-dts-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt

Ux500 DTS changes for the v4.20 kernel cycle.
Assorted housekeeping DTS patches.

* tag 'ux500-dts-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson

:
  ARM: dts: ux500: Mark PRCMU as syscon compatible
  arm: dts: ste: Update coresight bindings for hardware port
  ARM: dts: ste: Fix SPI controller node names
  ARM: dts: ux500: Get rid of DTC warnings
  ARM: dts: ux500: Fix LCDA clock line muxing
  dt-bindings: arm: scu: Correct example SCU unit addresses
  ARM: dts: ux500: Correct SCU unit address

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents da4cf9cd 3be9349f

Documentation/devicetree/bindings/arm/scu.txt

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ References: 


Example:



scu@a04100000 {

scu@a0410000 {

	compatible = "arm,cortex-a9-scu";

	reg = <0xa0410000 0x100>;

};

Documentation/devicetree/bindings/arm/ux500/boards.txt

+1 −1
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ Example: 
			      <0xa0410100 0x100>;

		};



		scu@a04100000 {

		scu@a0410000 {

			compatible = "arm,cortex-a9-scu";

			reg = <0xa0410000 0x100>;

		};

arch/arm/boot/dts/ste-dbx5x0.dtsi

+43 −37
Original line number Diff line number Diff line
@@ -15,9 +15,14 @@ 
#include <dt-bindings/arm/ux500_pm_domains.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/clock/ste-ab8500.h>

#include "skeleton.dtsi"



/ {

	#address-cells = <1>;

	#size-cells = <1>;



	chosen {

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -67,12 +72,14 @@ 
			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU0>;

			out-ports {

				port {

					ptm0_out_port: endpoint {

						remote-endpoint = <&funnel_in_port0>;

					};

				};

			};

		};



		ptm@801af000 {

			compatible = "arm,coresight-etm3x", "arm,primecell";
@@ -81,12 +88,14 @@ 
			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU1>;

			out-ports {

				port {

					ptm1_out_port: endpoint {

						remote-endpoint = <&funnel_in_port1>;

					};

				};

			};

		};



		funnel@801a6000 {

			compatible = "arm,coresight-funnel", "arm,primecell";
@@ -94,32 +103,29 @@ 


			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "apb_pclk", "atclk";

			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				/* funnel output ports */

				port@0 {

					reg = <0>;

			out-ports {

				port {

					funnel_out_port: endpoint {

						remote-endpoint =

							<&replicator_in_port0>;

					};

				};

			};



				/* funnel input ports */

				port@1 {

			in-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					funnel_in_port0: endpoint {

						slave-mode;

						remote-endpoint = <&ptm0_out_port>;

					};

				};



				port@2 {

				port@1 {

					reg = <1>;

					funnel_in_port1: endpoint {

						slave-mode;

						remote-endpoint = <&ptm1_out_port>;

					};

				};
@@ -131,11 +137,10 @@ 
			clocks = <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "atclk";



			ports {

			out-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				/* replicator output ports */

				port@0 {

					reg = <0>;

					replicator_out_port0: endpoint {
@@ -148,12 +153,11 @@ 
						remote-endpoint = <&etb_in_port>;

					};

				};

			};



				/* replicator input port */

				port@2 {

					reg = <0>;

			in-ports {

				port {

					replicator_in_port0: endpoint {

						slave-mode;

						remote-endpoint = <&funnel_out_port>;

					};

				};
@@ -166,13 +170,14 @@ 


			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "apb_pclk", "atclk";

			in-ports {

				port {

					tpiu_in_port: endpoint {

					slave-mode;

						remote-endpoint = <&replicator_out_port0>;

					};

				};

			};

		};



		etb@801a4000 {

			compatible = "arm,coresight-etb10", "arm,primecell";
@@ -180,13 +185,14 @@ 


			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "apb_pclk", "atclk";

			in-ports {

				port {

					etb_in_port: endpoint {

					slave-mode;

						remote-endpoint = <&replicator_out_port1>;

					};

				};

			};

		};



		intc: interrupt-controller@a0411000 {

			compatible = "arm,cortex-a9-gic";
@@ -197,7 +203,7 @@ 
			      <0xa0410100 0x100>;

		};



		scu@a04100000 {

		scu@a0410000 {

			compatible = "arm,cortex-a9-scu";

			reg = <0xa0410000 0x100>;

		};
@@ -487,7 +493,7 @@ 
		};



		prcmu: prcmu@80157000 {

			compatible = "stericsson,db8500-prcmu";

			compatible = "stericsson,db8500-prcmu", "syscon";

			reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;

			reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";

			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -878,7 +884,7 @@ 
			power-domains = <&pm_domains DOMAIN_VAPE>;

		};



		ssp@80002000 {

		spi@80002000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x80002000 0x1000>;

			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -892,7 +898,7 @@ 
			power-domains = <&pm_domains DOMAIN_VAPE>;

		};



		ssp@80003000 {

		spi@80003000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x80003000 0x1000>;

			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/ste-href-family-pinctrl.dtsi

+6 −2
Original line number Diff line number Diff line
@@ -607,16 +607,20 @@ 


			mcde {

				lcd_default_mode: lcd_default {

					default_mux {

					default_mux1 {

						/* Mux in VSI0 and all the data lines */

						function = "lcd";

						groups =

						"lcdvsi0_a_1", /* VSI0 for LCD */

						"lcd_d0_d7_a_1", /* Data lines */

						"lcd_d8_d11_a_1", /* TV-out */

						"lcdaclk_b_1", /* Clock line for TV-out */

						"lcdvsi1_a_1"; /* VSI1 for HDMI */

					};

					default_mux2 {

						function = "lcda";

						groups =

						"lcdaclk_b_1"; /* Clock line for TV-out */

					};

					default_cfg1 {

						pins =

						"GPIO68_E1", /* VSI0 */

arch/arm/boot/dts/ste-href.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 


/ {

	memory {

		device_type = "memory";

		reg = <0x00000000 0x20000000>;

	};

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