Commit 0e8e4fbf authored by Hersen Wu's avatar Hersen Wu Committed by Alex Deucher
Browse files

drm/amd/display: num of sw i2c/aux engines less than num of connectors 



[why]
AMD Stoney reference board, there are only 2 pipes (not include
underlay), and 3 connectors. resource creation, only
2 I2C/AUX engines are created. Within dc_link_aux_transfer, when
pin_data_en =2, refer to enengines[ddc_pin->pin_data->en] = NULL.
NULL point is referred later causing system crash.

[how]
each asic design has fixed number of ddc engines at hw side.
for each ddc engine, create its i2x/aux engine at sw side.

Signed-off-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 86a2da70

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+5 −1
Original line number Diff line number Diff line
@@ -372,7 +372,8 @@ static const struct resource_caps res_cap = { 
	.num_timing_generator = 6,

	.num_audio = 6,

	.num_stream_encoder = 6,

	.num_pll = 3

	.num_pll = 3,

	.num_ddc = 6,

};



#define CTX  ctx
@@ -1004,6 +1005,9 @@ static bool construct( 
				"DC: failed to create output pixel processor!\n");

			goto res_create_fail;

		}

	}



	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

		pool->base.engines[i] = dce100_aux_engine_create(ctx, i);

		if (pool->base.engines[i] == NULL) {

			BREAK_TO_DEBUGGER();

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

+4 −0
Original line number Diff line number Diff line
@@ -378,6 +378,7 @@ static const struct resource_caps carrizo_resource_cap = { 
		.num_audio = 3,

		.num_stream_encoder = 3,

		.num_pll = 2,

		.num_ddc = 3,

};



static const struct resource_caps stoney_resource_cap = {
@@ -386,6 +387,7 @@ static const struct resource_caps stoney_resource_cap = { 
		.num_audio = 3,

		.num_stream_encoder = 3,

		.num_pll = 2,

		.num_ddc = 3,

};



#define CTX  ctx
@@ -1336,7 +1338,9 @@ static bool construct( 
				"DC: failed to create output pixel processor!\n");

			goto res_create_fail;

		}

	}



	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

		pool->base.engines[i] = dce110_aux_engine_create(ctx, i);

		if (pool->base.engines[i] == NULL) {

			BREAK_TO_DEBUGGER();

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

+5 −0
Original line number Diff line number Diff line
@@ -384,6 +384,7 @@ static const struct resource_caps polaris_10_resource_cap = { 
		.num_audio = 6,

		.num_stream_encoder = 6,

		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */

		.num_ddc = 6,

};



static const struct resource_caps polaris_11_resource_cap = {
@@ -391,6 +392,7 @@ static const struct resource_caps polaris_11_resource_cap = { 
		.num_audio = 5,

		.num_stream_encoder = 5,

		.num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */

		.num_ddc = 5,

};



#define CTX  ctx
@@ -1286,6 +1288,9 @@ static bool construct( 
				"DC:failed to create output pixel processor!\n");

			goto res_create_fail;

		}

	}



	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

		pool->base.engines[i] = dce112_aux_engine_create(ctx, i);

		if (pool->base.engines[i] == NULL) {

			BREAK_TO_DEBUGGER();

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

+7 −2
Original line number Diff line number Diff line
@@ -436,6 +436,7 @@ static const struct resource_caps res_cap = { 
		.num_audio = 7,

		.num_stream_encoder = 6,

		.num_pll = 6,

		.num_ddc = 6,

};



static const struct dc_debug_options debug_defaults = {
@@ -1062,6 +1063,12 @@ static bool construct( 
			dm_error(

				"DC: failed to create output pixel processor!\n");

		}



		/* check next valid pipe */

		j++;

	}



	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

		pool->base.engines[i] = dce120_aux_engine_create(ctx, i);

		if (pool->base.engines[i] == NULL) {

			BREAK_TO_DEBUGGER();
@@ -1077,8 +1084,6 @@ static bool construct( 
			goto res_create_fail;

		}

		pool->base.sw_i2cs[i] = NULL;

		/* check next valid pipe */

		j++;

	}



	/* valid pipe num */

drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

+25 −0
Original line number Diff line number Diff line
@@ -367,6 +367,7 @@ static const struct resource_caps res_cap = { 
		.num_audio = 6,

		.num_stream_encoder = 6,

		.num_pll = 3,

		.num_ddc = 6,

};



static const struct resource_caps res_cap_81 = {
@@ -374,6 +375,7 @@ static const struct resource_caps res_cap_81 = { 
		.num_audio = 7,

		.num_stream_encoder = 7,

		.num_pll = 3,

		.num_ddc = 6,

};



static const struct resource_caps res_cap_83 = {
@@ -381,6 +383,7 @@ static const struct resource_caps res_cap_83 = { 
		.num_audio = 6,

		.num_stream_encoder = 6,

		.num_pll = 2,

		.num_ddc = 2,

};



static const struct dce_dmcu_registers dmcu_regs = {
@@ -992,7 +995,9 @@ static bool dce80_construct( 
			dm_error("DC: failed to create output pixel processor!\n");

			goto res_create_fail;

		}

	}



	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

		pool->base.engines[i] = dce80_aux_engine_create(ctx, i);

		if (pool->base.engines[i] == NULL) {

			BREAK_TO_DEBUGGER();
@@ -1200,6 +1205,16 @@ static bool dce81_construct( 
			dm_error("DC: failed to create output pixel processor!\n");

			goto res_create_fail;

		}

	}



	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

		pool->base.engines[i] = dce80_aux_engine_create(ctx, i);

		if (pool->base.engines[i] == NULL) {

			BREAK_TO_DEBUGGER();

			dm_error(

				"DC:failed to create aux engine!!\n");

			goto res_create_fail;

		}

		pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);

		if (pool->base.hw_i2cs[i] == NULL) {

			BREAK_TO_DEBUGGER();
@@ -1396,6 +1411,16 @@ static bool dce83_construct( 
			dm_error("DC: failed to create output pixel processor!\n");

			goto res_create_fail;

		}

	}



	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {

		pool->base.engines[i] = dce80_aux_engine_create(ctx, i);

		if (pool->base.engines[i] == NULL) {

			BREAK_TO_DEBUGGER();

			dm_error(

				"DC:failed to create aux engine!!\n");

			goto res_create_fail;

		}

		pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);

		if (pool->base.hw_i2cs[i] == NULL) {

			BREAK_TO_DEBUGGER();

CRA Git | Maintained and supported by SUSTech CRA and CCSE