Commit 0e37f88d authored by Maxime Ripard's avatar Maxime Ripard Committed by Linus Walleij
Browse files

ARM: sunxi: Add pinctrl driver for Allwinner SoCs 



The Allwinner SoCs have an IP module that handle both the muxing and the
GPIOs.

This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC used on the board.

This driver only implements the pinctrl part, the gpio part will come
eventually.

Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarOlof Johansson <olof@lixom.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 9931faca

Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt

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* Allwinner A1X Pin Controller



The pins controlled by sunXi pin controller are organized in banks,

each bank has 32 pins.  Each pin has 7 multiplexing functions, with

the first two functions being GPIO in and out. The configuration on

the pins includes drive strength and pull-up.



Required properties:

- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are:

  sun5i-a13.

- reg: Should contain the register physical address and length for the

  pin controller.



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices.



A pinctrl node should contain at least one subnodes representing the

pinctrl groups available on the machine. Each subnode will list the

pins it needs, and how they should be configured, with regard to muxer

configuration, drive strength and pullups. If one of these options is

not set, its actual value will be unspecified.



Required subnode-properties:



- allwinner,pins: List of strings containing the pin name.

- allwinner,function: Function to mux the pins listed above to.



Optional subnode-properties:

- allwinner,drive: Integer. Represents the current sent to the pin

    0: 10 mA

    1: 20 mA

    2: 30 mA

    3: 40 mA

- allwinner,pull: Integer.

    0: No resistor

    1: Pull-up resistor

    2: Pull-down resistor



Examples:



pinctrl@01c20800 {

	compatible = "allwinner,sun5i-a13-pinctrl";

	reg = <0x01c20800 0x400>;

	#address-cells = <1>;

	#size-cells = <0>;



	uart1_pins_a: uart1@0 {

		allwinner,pins = "PE10", "PE11";

		allwinner,function = "uart1";

		allwinner,drive = <0>;

		allwinner,pull = <0>;

	};



	uart1_pins_b: uart1@1 {

		allwinner,pins = "PG3", "PG4";

		allwinner,function = "uart1";

		allwinner,drive = <0>;

		allwinner,pull = <0>;

	};

};

arch/arm/mach-sunxi/Kconfig

+1 −0
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@@ -7,3 +7,4 @@ config ARCH_SUNXI 
	select PINCTRL

	select SPARSE_IRQ

	select SUNXI_TIMER

	select PINCTRL_SUNXI
 
 No newline at end of file

drivers/pinctrl/Kconfig

+5 −0
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@@ -151,6 +151,11 @@ config PINCTRL_SIRF 
	depends on ARCH_SIRF

	select PINMUX



config PINCTRL_SUNXI

	bool

	select PINMUX

	select GENERIC_PINCONF



config PINCTRL_TEGRA

	bool

	select PINMUX

drivers/pinctrl/Makefile

+1 −0
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@@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 
obj-$(CONFIG_PINCTRL_PXA910)	+= pinctrl-pxa910.o

obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o

obj-$(CONFIG_PINCTRL_SIRF)	+= pinctrl-sirf.o

obj-$(CONFIG_PINCTRL_SUNXI)	+= pinctrl-sunxi.o

obj-$(CONFIG_PINCTRL_TEGRA)	+= pinctrl-tegra.o

obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o

obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o

drivers/pinctrl/pinctrl-sunxi.c

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/*

 * Allwinner A1X SoCs pinctrl driver.

 *

 * Copyright (C) 2012 Maxime Ripard

 *

 * Maxime Ripard <maxime.ripard@free-electrons.com>

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



#include <linux/io.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/pinctrl/consumer.h>

#include <linux/pinctrl/machine.h>

#include <linux/pinctrl/pinctrl.h>

#include <linux/pinctrl/pinconf-generic.h>

#include <linux/pinctrl/pinmux.h>

#include <linux/platform_device.h>

#include <linux/slab.h>



#include "core.h"

#include "pinctrl-sunxi.h"



static struct sunxi_pinctrl_group *

sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)

{

	int i;



	for (i = 0; i < pctl->ngroups; i++) {

		struct sunxi_pinctrl_group *grp = pctl->groups + i;



		if (!strcmp(grp->name, group))

			return grp;

	}



	return NULL;

}



static struct sunxi_pinctrl_function *

sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,

				    const char *name)

{

	struct sunxi_pinctrl_function *func = pctl->functions;

	int i;



	for (i = 0; i < pctl->nfunctions; i++) {

		if (!func[i].name)

			break;



		if (!strcmp(func[i].name, name))

			return func + i;

	}



	return NULL;

}



static struct sunxi_desc_function *

sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,

					 const char *pin_name,

					 const char *func_name)

{

	int i;



	for (i = 0; i < pctl->desc->npins; i++) {

		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;



		if (!strcmp(pin->pin.name, pin_name)) {

			struct sunxi_desc_function *func = pin->functions;



			while (func->name) {

				if (!strcmp(func->name, func_name))

					return func;



				func++;

			}

		}

	}



	return NULL;

}



static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);



	return pctl->ngroups;

}



static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,

					      unsigned group)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);



	return pctl->groups[group].name;

}



static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,

				      unsigned group,

				      const unsigned **pins,

				      unsigned *num_pins)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);



	*pins = (unsigned *)&pctl->groups[group].pin;

	*num_pins = 1;



	return 0;

}



static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,

				      struct device_node *node,

				      struct pinctrl_map **map,

				      unsigned *num_maps)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);

	unsigned long *pinconfig;

	struct property *prop;

	const char *function;

	const char *group;

	int ret, nmaps, i = 0;

	u32 val;



	*map = NULL;

	*num_maps = 0;



	ret = of_property_read_string(node, "allwinner,function", &function);

	if (ret) {

		dev_err(pctl->dev,

			"missing allwinner,function property in node %s\n",

			node->name);

		return -EINVAL;

	}



	nmaps = of_property_count_strings(node, "allwinner,pins") * 2;

	if (nmaps < 0) {

		dev_err(pctl->dev,

			"missing allwinner,pins property in node %s\n",

			node->name);

		return -EINVAL;

	}



	*map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);

	if (!map)

		return -ENOMEM;



	of_property_for_each_string(node, "allwinner,pins", prop, group) {

		struct sunxi_pinctrl_group *grp =

			sunxi_pinctrl_find_group_by_name(pctl, group);

		int j = 0, configlen = 0;



		if (!grp) {

			dev_err(pctl->dev, "unknown pin %s", group);

			continue;

		}



		if (!sunxi_pinctrl_desc_find_function_by_name(pctl,

							      grp->name,

							      function)) {

			dev_err(pctl->dev, "unsupported function %s on pin %s",

				function, group);

			continue;

		}



		(*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;

		(*map)[i].data.mux.group = group;

		(*map)[i].data.mux.function = function;



		i++;



		(*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;

		(*map)[i].data.configs.group_or_pin = group;



		if (of_find_property(node, "allwinner,drive", NULL))

			configlen++;

		if (of_find_property(node, "allwinner,pull", NULL))

			configlen++;



		pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);



		if (!of_property_read_u32(node, "allwinner,drive", &val)) {

			u16 strength = (val + 1) * 10;

			pinconfig[j++] =

				pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,

							 strength);

		}



		if (!of_property_read_u32(node, "allwinner,pull", &val)) {

			enum pin_config_param pull = PIN_CONFIG_END;

			if (val == 1)

				pull = PIN_CONFIG_BIAS_PULL_UP;

			else if (val == 2)

				pull = PIN_CONFIG_BIAS_PULL_DOWN;

			pinconfig[j++] = pinconf_to_config_packed(pull, 0);

		}



		(*map)[i].data.configs.configs = pinconfig;

		(*map)[i].data.configs.num_configs = configlen;



		i++;

	}



	*num_maps = nmaps;



	return 0;

}



static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,

				    struct pinctrl_map *map,

				    unsigned num_maps)

{

	int i;



	for (i = 0; i < num_maps; i++) {

		if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)

			kfree(map[i].data.configs.configs);

	}



	kfree(map);

}



static struct pinctrl_ops sunxi_pctrl_ops = {

	.dt_node_to_map		= sunxi_pctrl_dt_node_to_map,

	.dt_free_map		= sunxi_pctrl_dt_free_map,

	.get_groups_count	= sunxi_pctrl_get_groups_count,

	.get_group_name		= sunxi_pctrl_get_group_name,

	.get_group_pins		= sunxi_pctrl_get_group_pins,

};



static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,

				 unsigned group,

				 unsigned long *config)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);



	*config = pctl->groups[group].config;



	return 0;

}



static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,

				 unsigned group,

				 unsigned long config)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);

	struct sunxi_pinctrl_group *g = &pctl->groups[group];

	u32 val, mask;

	u16 strength;

	u8 dlevel;



	switch (pinconf_to_config_param(config)) {

	case PIN_CONFIG_DRIVE_STRENGTH:

		strength = pinconf_to_config_argument(config);

		if (strength > 40)

			return -EINVAL;

		/*

		 * We convert from mA to what the register expects:

		 *   0: 10mA

		 *   1: 20mA

		 *   2: 30mA

		 *   3: 40mA

		 */

		dlevel = strength / 10 - 1;

		val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));

	        mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);

		writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin),

			pctl->membase + sunxi_dlevel_reg(g->pin));

		break;

	case PIN_CONFIG_BIAS_PULL_UP:

		val = readl(pctl->membase + sunxi_pull_reg(g->pin));

		mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);

		writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),

			pctl->membase + sunxi_pull_reg(g->pin));

		break;

	case PIN_CONFIG_BIAS_PULL_DOWN:

		val = readl(pctl->membase + sunxi_pull_reg(g->pin));

		mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);

		writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),

			pctl->membase + sunxi_pull_reg(g->pin));

		break;

	default:

		break;

	}



	/* cache the config value */

	g->config = config;



	return 0;

}



static struct pinconf_ops sunxi_pconf_ops = {

	.pin_config_group_get	= sunxi_pconf_group_get,

	.pin_config_group_set	= sunxi_pconf_group_set,

};



static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);



	return pctl->nfunctions;

}



static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,

					   unsigned function)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);



	return pctl->functions[function].name;

}



static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,

				     unsigned function,

				     const char * const **groups,

				     unsigned * const num_groups)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);



	*groups = pctl->functions[function].groups;

	*num_groups = pctl->functions[function].ngroups;



	return 0;

}



static void sunxi_pmx_set(struct pinctrl_dev *pctldev,

				 unsigned pin,

				 u8 config)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);



	u32 val = readl(pctl->membase + sunxi_mux_reg(pin));

	u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);

	writel((val & ~mask) | config << sunxi_mux_offset(pin),

		pctl->membase + sunxi_mux_reg(pin));

}



static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,

			    unsigned function,

			    unsigned group)

{

	struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);

	struct sunxi_pinctrl_group *g = pctl->groups + group;

	struct sunxi_pinctrl_function *func = pctl->functions + function;

	struct sunxi_desc_function *desc =

		sunxi_pinctrl_desc_find_function_by_name(pctl,

							 g->name,

							 func->name);



	if (!desc)

		return -EINVAL;



	sunxi_pmx_set(pctldev, g->pin, desc->muxval);



	return 0;

}



static struct pinmux_ops sunxi_pmx_ops = {

	.get_functions_count	= sunxi_pmx_get_funcs_cnt,

	.get_function_name	= sunxi_pmx_get_func_name,

	.get_function_groups	= sunxi_pmx_get_func_groups,

	.enable			= sunxi_pmx_enable,

};



static struct pinctrl_desc sunxi_pctrl_desc = {

	.confops	= &sunxi_pconf_ops,

	.pctlops	= &sunxi_pctrl_ops,

	.pmxops		= &sunxi_pmx_ops,

};



static struct of_device_id sunxi_pinctrl_match[] = {

	{}

};

MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);



static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,

					const char *name)

{

	struct sunxi_pinctrl_function *func = pctl->functions;



	while (func->name) {

		/* function already there */

		if (strcmp(func->name, name) == 0) {

			func->ngroups++;

			return -EEXIST;

		}

		func++;

	}



	func->name = name;

	func->ngroups = 1;



	pctl->nfunctions++;



	return 0;

}



static int sunxi_pinctrl_build_state(struct platform_device *pdev)

{

	struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);

	int i;



	pctl->ngroups = pctl->desc->npins;



	/* Allocate groups */

	pctl->groups = devm_kzalloc(&pdev->dev,

				    pctl->ngroups * sizeof(*pctl->groups),

				    GFP_KERNEL);

	if (!pctl->groups)

		return -ENOMEM;



	for (i = 0; i < pctl->desc->npins; i++) {

		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;

		struct sunxi_pinctrl_group *group = pctl->groups + i;



		group->name = pin->pin.name;

		group->pin = pin->pin.number;

	}



	/*

	 * We suppose that we won't have any more functions than pins,

	 * we'll reallocate that later anyway

	 */

	pctl->functions = devm_kzalloc(&pdev->dev,

				pctl->desc->npins * sizeof(*pctl->functions),

				GFP_KERNEL);

	if (!pctl->functions)

		return -ENOMEM;



	/* Count functions and their associated groups */

	for (i = 0; i < pctl->desc->npins; i++) {

		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;

		struct sunxi_desc_function *func = pin->functions;



		while (func->name) {

			sunxi_pinctrl_add_function(pctl, func->name);

			func++;

		}

	}



	pctl->functions = krealloc(pctl->functions,

				pctl->nfunctions * sizeof(*pctl->functions),

				GFP_KERNEL);



	for (i = 0; i < pctl->desc->npins; i++) {

		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;

		struct sunxi_desc_function *func = pin->functions;



		while (func->name) {

			struct sunxi_pinctrl_function *func_item;

			const char **func_grp;



			func_item = sunxi_pinctrl_find_function_by_name(pctl,

									func->name);

			if (!func_item)

				return -EINVAL;



			if (!func_item->groups) {

				func_item->groups =

					devm_kzalloc(&pdev->dev,

						     func_item->ngroups * sizeof(*func_item->groups),

						     GFP_KERNEL);

				if (!func_item->groups)

					return -ENOMEM;

			}



			func_grp = func_item->groups;

			while (*func_grp)

				func_grp++;



			*func_grp = pin->pin.name;

			func++;

		}

	}



	return 0;

}



static int sunxi_pinctrl_probe(struct platform_device *pdev)

{

	struct device_node *node = pdev->dev.of_node;

	const struct of_device_id *device;

	struct pinctrl_pin_desc *pins;

	struct sunxi_pinctrl *pctl;

	int i, ret;



	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);

	if (!pctl)

		return -ENOMEM;

	platform_set_drvdata(pdev, pctl);



	pctl->membase = of_iomap(node, 0);

	if (!pctl->membase)

		return -ENOMEM;



	device = of_match_device(sunxi_pinctrl_match, &pdev->dev);

	if (!device)

		return -ENODEV;



	pctl->desc = (struct sunxi_pinctrl_desc *)device->data;



	ret = sunxi_pinctrl_build_state(pdev);

	if (ret) {

		dev_err(&pdev->dev, "dt probe failed: %d\n", ret);

		return ret;

	}



	pins = devm_kzalloc(&pdev->dev,

			    pctl->desc->npins * sizeof(*pins),

			    GFP_KERNEL);

	if (!pins)

		return -ENOMEM;



	for (i = 0; i < pctl->desc->npins; i++)

		pins[i] = pctl->desc->pins[i].pin;



	sunxi_pctrl_desc.name = dev_name(&pdev->dev);

	sunxi_pctrl_desc.owner = THIS_MODULE;

	sunxi_pctrl_desc.pins = pins;

	sunxi_pctrl_desc.npins = pctl->desc->npins;

	pctl->dev = &pdev->dev;

	pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,

					  &pdev->dev, pctl);

	if (!pctl->pctl_dev) {

		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");

		return -EINVAL;

	}



	dev_info(&pdev->dev, "initialized sunXi pin control driver\n");



	return 0;

}



static struct platform_driver sunxi_pinctrl_driver = {

	.probe = sunxi_pinctrl_probe,

	.driver = {

		.name = "sunxi-pinctrl",

		.owner = THIS_MODULE,

		.of_match_table = sunxi_pinctrl_match,

	},

};

module_platform_driver(sunxi_pinctrl_driver);



MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");

MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");

MODULE_LICENSE("GPL");

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