Commit 0e2e45e2 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
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perf/x86: Add a macro for RDPMC offset of fixed counters 



The RDPMC base offset of fixed counters is hard-code. Use a meaningful
name to replace the magic number to improve the readability of the code.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200723171117.9918-10-kan.liang@linux.intel.com
parent 7b2c05a1

arch/x86/events/core.c

+2 −1
Original line number Diff line number Diff line
@@ -1151,7 +1151,8 @@ static inline void x86_assign_hw_event(struct perf_event *event, 
		hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;

		hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +

				(idx - INTEL_PMC_IDX_FIXED);

		hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) | 1<<30;

		hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |

					INTEL_PMC_FIXED_RDPMC_BASE;

		break;



	default:

arch/x86/include/asm/perf_event.h

+3 −0
Original line number Diff line number Diff line
@@ -196,6 +196,9 @@ struct x86_pmu_capability { 
 * Fixed-purpose performance events:

 */



/* RDPMC offset for Fixed PMCs */

#define INTEL_PMC_FIXED_RDPMC_BASE		(1 << 30)



/*

 * All the fixed-mode PMCs are configured via this single MSR:

 */

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