Merge tag 'nand/fixes-for-4.9-rc3' of github.com:linux-nand/linux

Date:           October 2014

Contact:        linuxppc-dev@lists.ozlabs.org

Description:    write only

                Writing 1 will issue a PERST to card which may cause the card

                to reload the FPGA depending on load_image_on_perst.

                Writing 1 will issue a PERST to card provided there are no

                contexts active on any one of the card AFUs. This may cause

                the card to reload the FPGA depending on load_image_on_perst.

                Writing -1 will do a force PERST irrespective of any active

                contexts on the card AFUs.

Users:		https://github.com/ibm-capi/libcxl

What:		/sys/class/cxl/<card>/perst_reloads_same_image (not in a guest)

* Aspeed BT (Block Transfer) IPMI interface

The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs

(BaseBoard Management Controllers) and the BT interface can be used to

perform in-band IPMI communication with their host.

Required properties:

- compatible : should be "aspeed,ast2400-bt-bmc"

- reg: physical address and size of the registers

Optional properties:

- interrupts: interrupt generated by the BT interface. without an

  interrupt, the driver will operate in poll mode.

Example:

	ibt@1e789140 {

		compatible = "aspeed,ast2400-bt-bmc";

		reg = <0x1e789140 0x18>;

		interrupts = <8>;

	};

GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8

I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7

RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8

RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6

TIMER7 TIMER8 VGABIOSROM

Examples:

J-Core Programmable Interval Timer and Clocksource

Required properties:

- compatible: Must be "jcore,pit".

- reg: Memory region(s) for timer/clocksource registers. For SMP,

  there should be one region per cpu, indexed by the sequential,

  zero-based hardware cpu number.

- interrupts: An interrupt to assign for the timer. The actual pit

  core is integrated with the aic and allows the timer interrupt

  assignment to be programmed by software, but this property is

  required in order to reserve an interrupt number that doesn't

  conflict with other devices.

Example:

timer@200 {

	compatible = "jcore,pit";

	reg = < 0x200 0x30 0x500 0x30 >;

	interrupts = < 0x48 >;

};