net: aquantia: definitions for WOL (0e1a0dde) · Commits · 戴 / test

drivers/net/ethernet/aquantia/atlantic/aq_nic.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -36,6 +36,7 @@ struct aq_nic_cfg_s {
		u32 flow_control;
		u32 link_speed_msk;
		u32 vlan_id;
		u32 wol;
		u16 is_mc_list_enabled;
		u16 mc_list_count;
		bool is_autoneg;
		@@ -54,6 +55,8 @@ struct aq_nic_cfg_s {
		#define AQ_NIC_FLAG_ERR_UNPLUG 0x40000000U
		#define AQ_NIC_FLAG_ERR_HW 0x80000000U

		#define AQ_NIC_WOL_ENABLED BIT(0)

		#define AQ_NIC_TCVEC2RING(_NIC_, _TC_, _VEC_) \
		((_TC_) * AQ_CFG_TCS_MAX + (_VEC_))

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h

+89 −5

Original line number	Diff line number	Diff line
		@@ -101,8 +101,6 @@ struct __packed hw_aq_atl_utils_fw_rpc {
		struct {
		u32 priority;
		u32 wol_packet_type;
		u16 friendly_name_len;
		u16 friendly_name[65];
		u32 pattern_id;
		u32 next_wol_pattern_offset;

		@@ -134,13 +132,36 @@ struct __packed hw_aq_atl_utils_fw_rpc {
		u32 pattern_offset;
		u32 pattern_size;
		} wol_bit_map_pattern;

		struct {
		u8 mac_addr[ETH_ALEN];
		} wol_magic_packet_patter;
		} wol_pattern;
		} msg_wol;

		struct {
		u32 is_wake_on_link_down;
		u32 is_wake_on_link_up;
		} msg_wolink;
		union {
		u32 pattern_mask;

		struct {
		u32 reason_arp_v4_pkt : 1;
		u32 reason_ipv4_ping_pkt : 1;
		u32 reason_ipv6_ns_pkt : 1;
		u32 reason_ipv6_ping_pkt : 1;
		u32 reason_link_up : 1;
		u32 reason_link_down : 1;
		u32 reason_maximum : 1;
		};
		};

		union {
		u32 offload_mask;
		};
		} msg_enable_wakeup;

		struct {
		u32 id;
		} msg_del_id;
		};
		};

		@@ -155,6 +176,57 @@ struct __packed hw_aq_atl_utils_mbox {
		struct hw_atl_stats_s stats;
		};

		/* fw2x */
		typedef u32 fw_offset_t;

		struct __packed offload_ip_info {
		u8 v4_local_addr_count;
		u8 v4_addr_count;
		u8 v6_local_addr_count;
		u8 v6_addr_count;
		fw_offset_t v4_addr;
		fw_offset_t v4_prefix;
		fw_offset_t v6_addr;
		fw_offset_t v6_prefix;
		};

		struct __packed offload_port_info {
		u16 udp_port_count;
		u16 tcp_port_count;
		fw_offset_t udp_port;
		fw_offset_t tcp_port;
		};

		struct __packed offload_ka_info {
		u16 v4_ka_count;
		u16 v6_ka_count;
		u32 retry_count;
		u32 retry_interval;
		fw_offset_t v4_ka;
		fw_offset_t v6_ka;
		};

		struct __packed offload_rr_info {
		u32 rr_count;
		u32 rr_buf_len;
		fw_offset_t rr_id_x;
		fw_offset_t rr_buf;
		};

		struct __packed offload_info {
		u32 version;
		u32 len;
		u8 mac_addr[ETH_ALEN];

		u8 reserved[2];

		struct offload_ip_info ips;
		struct offload_port_info ports;
		struct offload_ka_info kas;
		struct offload_rr_info rrs;
		u8 buf[0];
		};

		#define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U
		#define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U
		#define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U
		@@ -181,6 +253,18 @@ enum hal_atl_utils_fw_state_e {
		#define HAL_ATLANTIC_RATE_100M BIT(5)
		#define HAL_ATLANTIC_RATE_INVALID BIT(6)

		#define HAL_ATLANTIC_UTILS_FW_MSG_PING 0x1U
		#define HAL_ATLANTIC_UTILS_FW_MSG_ARP 0x2U
		#define HAL_ATLANTIC_UTILS_FW_MSG_INJECT 0x3U
		#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD 0x4U
		#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL 0x5U
		#define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 0x6U
		#define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC 0x7U
		#define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING 0x8U
		#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD 0x9U
		#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL 0xAU
		#define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG 0xDU

		enum hw_atl_fw2x_rate {
		FW2X_RATE_100M = 0x20,
		FW2X_RATE_1G = 0x100,

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c

+32 −0

Original line number	Diff line number	Diff line
		@@ -16,6 +16,7 @@
		#include "../aq_pci_func.h"
		#include "../aq_ring.h"
		#include "../aq_vec.h"
		#include "../aq_nic.h"
		#include "hw_atl_utils.h"
		#include "hw_atl_llh.h"

		@@ -29,6 +30,37 @@
		#define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
		#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374

		#define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY)
		#define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL)

		#define HW_ATL_FW2X_CTRL_SLEEP_PROXY BIT(CTRL_SLEEP_PROXY)
		#define HW_ATL_FW2X_CTRL_WOL BIT(CTRL_WOL)
		#define HW_ATL_FW2X_CTRL_LINK_DROP BIT(CTRL_LINK_DROP)
		#define HW_ATL_FW2X_CTRL_PAUSE BIT(CTRL_PAUSE)
		#define HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE BIT(CTRL_ASYMMETRIC_PAUSE)
		#define HW_ATL_FW2X_CTRL_FORCE_RECONNECT BIT(CTRL_FORCE_RECONNECT)

		#define HAL_ATLANTIC_WOL_FILTERS_COUNT 8
		#define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E

		struct __packed fw2x_msg_wol_pattern {
		u8 mask[16];
		u32 crc;
		};

		struct __packed fw2x_msg_wol {
		u32 msg_id;
		u8 hw_addr[ETH_ALEN];
		u8 magic_packet_enabled;
		u8 filter_count;
		struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
		u8 link_up_enabled;
		u8 link_down_enabled;
		u16 reserved;
		u32 link_up_timeout;
		u32 link_down_timeout;
		};

		static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
		static int aq_fw2x_set_state(struct aq_hw_s *self,
		enum hal_atl_utils_fw_state_e state);

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