Commit 0dfb3b41 authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
Browse files

serial: samsung: merge all SoC specific port reset functions 



The port reset function in each of the platform specific extension performs
the same operations and hence all the reset port functions can be merged into
one and moved into the common samsung uart driver. The SoC specific port reset
functions are removed from SoC extensions.

Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 0cfb26e1

drivers/tty/serial/s3c2410.c

+0 −18
Original line number Diff line number Diff line
@@ -25,23 +25,6 @@ 


#include "samsung.h"



static int s3c2410_serial_resetport(struct uart_port *port,

				    struct s3c2410_uartcfg *cfg)

{

	dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",

	    port, port->mapbase, cfg);



	wr_regl(port, S3C2410_UCON,  cfg->ucon);

	wr_regl(port, S3C2410_ULCON, cfg->ulcon);



	/* reset both fifos */



	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);

	wr_regl(port, S3C2410_UFCON, cfg->ufcon);



	return 0;

}



static struct s3c24xx_uart_info s3c2410_uart_inf = {

	.name		= "Samsung S3C2410 UART",

	.type		= PORT_S3C2410,
@@ -56,7 +39,6 @@ static struct s3c24xx_uart_info s3c2410_uart_inf = { 
	.num_clks	= 2,

	.clksel_mask	= S3C2410_UCON_CLKMASK,

	.clksel_shift	= S3C2410_UCON_CLKSHIFT,

	.reset_port	= s3c2410_serial_resetport,

};



static int s3c2410_serial_probe(struct platform_device *dev)

drivers/tty/serial/s3c2412.c

+0 −24
Original line number Diff line number Diff line
@@ -25,29 +25,6 @@ 


#include "samsung.h"



static int s3c2412_serial_resetport(struct uart_port *port,

				    struct s3c2410_uartcfg *cfg)

{

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	dbg("%s: port=%p (%08lx), cfg=%p\n",

	    __func__, port, port->mapbase, cfg);



	/* ensure we don't change the clock settings... */



	ucon &= S3C2412_UCON_CLKMASK;



	wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);

	wr_regl(port, S3C2410_ULCON, cfg->ulcon);



	/* reset both fifos */



	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);

	wr_regl(port, S3C2410_UFCON, cfg->ufcon);



	return 0;

}



static struct s3c24xx_uart_info s3c2412_uart_inf = {

	.name		= "Samsung S3C2412 UART",

	.type		= PORT_S3C2412,
@@ -63,7 +40,6 @@ static struct s3c24xx_uart_info s3c2412_uart_inf = { 
	.num_clks	= 4,

	.clksel_mask	= S3C2412_UCON_CLKMASK,

	.clksel_shift	= S3C2412_UCON_CLKSHIFT,

	.reset_port	= s3c2412_serial_resetport,

};



/* device management */

drivers/tty/serial/s3c2440.c

+0 −24
Original line number Diff line number Diff line
@@ -25,29 +25,6 @@ 


#include "samsung.h"



static int s3c2440_serial_resetport(struct uart_port *port,

				    struct s3c2410_uartcfg *cfg)

{

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",

	    port, port->mapbase, cfg);



	/* ensure we don't change the clock settings... */



	ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));



	wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);

	wr_regl(port, S3C2410_ULCON, cfg->ulcon);



	/* reset both fifos */



	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);

	wr_regl(port, S3C2410_UFCON, cfg->ufcon);



	return 0;

}



static struct s3c24xx_uart_info s3c2440_uart_inf = {

	.name		= "Samsung S3C2440 UART",

	.type		= PORT_S3C2440,
@@ -62,7 +39,6 @@ static struct s3c24xx_uart_info s3c2440_uart_inf = { 
	.num_clks	= 4,

	.clksel_mask	= S3C2440_UCON_CLKMASK,

	.clksel_shift	= S3C2440_UCON_CLKSHIFT,

	.reset_port	= s3c2440_serial_resetport,

};



/* device management */

drivers/tty/serial/s3c6400.c

+0 −24
Original line number Diff line number Diff line
@@ -26,29 +26,6 @@ 


#include "samsung.h"



static int s3c6400_serial_resetport(struct uart_port *port,

				    struct s3c2410_uartcfg *cfg)

{

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",

	    port, port->mapbase, cfg);



	/* ensure we don't change the clock settings... */



	ucon &= S3C6400_UCON_CLKMASK;



	wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);

	wr_regl(port, S3C2410_ULCON, cfg->ulcon);



	/* reset both fifos */



	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);

	wr_regl(port, S3C2410_UFCON, cfg->ufcon);



	return 0;

}



static struct s3c24xx_uart_info s3c6400_uart_inf = {

	.name		= "Samsung S3C6400 UART",

	.type		= PORT_S3C6400,
@@ -64,7 +41,6 @@ static struct s3c24xx_uart_info s3c6400_uart_inf = { 
	.num_clks	= 4,

	.clksel_mask	= S3C6400_UCON_CLKMASK,

	.clksel_shift	= S3C6400_UCON_CLKSHIFT,

	.reset_port	= s3c6400_serial_resetport,

};



/* device management */

drivers/tty/serial/s5pv210.c

+1 −21
Original line number Diff line number Diff line
@@ -25,25 +25,6 @@ 
#include <plat/regs-serial.h>

#include "samsung.h"



static int s5pv210_serial_resetport(struct uart_port *port,

					struct s3c2410_uartcfg *cfg)

{

	unsigned long ucon = rd_regl(port, S3C2410_UCON);



	ucon &= S5PV210_UCON_CLKMASK;

	wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);

	wr_regl(port, S3C2410_ULCON, cfg->ulcon);



	/* reset both fifos */

	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);

	wr_regl(port, S3C2410_UFCON, cfg->ufcon);



	/* It is need to delay When reset FIFO register */

	udelay(1);



	return 0;

}



#define S5PV210_UART_DEFAULT_INFO(fifo_size)			\

		.name		= "Samsung S5PV210 UART0",	\

		.type		= PORT_S3C6400,			\
@@ -58,8 +39,7 @@ static int s5pv210_serial_resetport(struct uart_port *port, 
		.def_clk_sel	= S3C2410_UCON_CLKSEL0,		\

		.num_clks	= 2,				\

		.clksel_mask	= S5PV210_UCON_CLKMASK,		\

		.clksel_shift	= S5PV210_UCON_CLKSHIFT,	\

		.reset_port	= s5pv210_serial_resetport

		.clksel_shift	= S5PV210_UCON_CLKSHIFT



static struct s3c24xx_uart_info s5p_port_fifo256 = {

	S5PV210_UART_DEFAULT_INFO(256),

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