Commit 0db7f5cd authored Jun 18, 2019 by ShihPo Hung Committed by Paul Walmsley Jun 26, 2019

riscv: mm: Fix code comment



Fix the comment since vmalloc_fault doesn't reach
flush_tlb_fix_spurious_fault.

Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: linux-riscv@lists.infradead.org
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>

parent e3f9dada

arch/riscv/mm/fault.c

+0 −3

Original line number	Diff line number	Diff line
		@@ -272,9 +272,6 @@ vmalloc_fault:
		* entries, but in RISC-V, SFENCE.VMA specifies an
		* ordering constraint, not a cache flush; it is
		* necessary even after writing invalid entries.
		* Relying on flush_tlb_fix_spurious_fault would
		* suffice, but the extra traps reduce
		* performance. So, eagerly SFENCE.VMA.
		*/
		local_flush_tlb_page(addr);

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