drm/amdgpu: use same vce state definition in dpm and powerplay (0d8de7ca) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -554,7 +554,7 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
		((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record));
		}
		for (i = 0; i < states->numEntries; i++) {
		if (i >= AMDGPU_MAX_VCE_LEVELS)
		if (i >= AMD_MAX_VCE_LEVELS)
		break;
		vce_clk = (VCEClockInfo *)
		((u8 *)&array->entries[0] +

drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h

+3 −25

Original line number	Diff line number	Diff line
		@@ -52,17 +52,6 @@ enum amdgpu_dpm_event_src {
		AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
		};

		#define AMDGPU_MAX_VCE_LEVELS 6

		enum amdgpu_vce_level {
		AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
		AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
		AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
		AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
		AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
		AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
		};

		struct amdgpu_ps {
		u32 caps; /* vbios flags */
		u32 class; /* vbios flags */
		@@ -74,7 +63,7 @@ struct amdgpu_ps {
		u32 evclk;
		u32 ecclk;
		bool vce_active;
		enum amdgpu_vce_level vce_level;
		enum amd_vce_level vce_level;
		/* asic priv */
		void *ps_priv;
		};
		@@ -257,17 +246,6 @@ enum amdgpu_dpm_forced_level {
		AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
		};

		struct amdgpu_vce_state {
		/* vce clocks */
		u32 evclk;
		u32 ecclk;
		/* gpu clocks */
		u32 sclk;
		u32 mclk;
		u8 clk_idx;
		u8 pstate;
		};

		struct amdgpu_dpm_funcs {
		int (get_temperature)(struct amdgpu_device adev);
		int (pre_set_power_state)(struct amdgpu_device adev);
		@@ -409,8 +387,8 @@ struct amdgpu_dpm {
		/* default uvd power state */
		struct amdgpu_ps *uvd_ps;
		/* vce requirements */
		struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
		enum amdgpu_vce_level vce_level;
		struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
		enum amd_vce_level vce_level;
		enum amd_pm_state_type state;
		enum amd_pm_state_type user_state;
		u32 platform_caps;

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1135,7 +1135,7 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
		mutex_lock(&adev->pm.mutex);
		adev->pm.dpm.vce_active = true;
		/* XXX select vce level based on ring/task */
		adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
		adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
		mutex_unlock(&adev->pm.mutex);
		} else {
		mutex_lock(&adev->pm.mutex);

drivers/gpu/drm/amd/amdgpu/ci_dpm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -5689,7 +5689,7 @@ static int ci_parse_power_table(struct amdgpu_device *adev)
		adev->pm.dpm.num_ps = state_array->ucNumEntries;

		/* fill in the vce power states */
		for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
		for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) {
		u32 sclk, mclk;
		clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
		clock_info = (union pplib_clock_info *)

drivers/gpu/drm/amd/amdgpu/kv_dpm.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -2796,7 +2796,7 @@ static int kv_parse_power_table(struct amdgpu_device *adev)
		adev->pm.dpm.num_ps = state_array->ucNumEntries;

		/* fill in the vce power states */
		for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
		for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) {
		u32 sclk;
		clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
		clock_info = (union pplib_clock_info *)

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