Commit 0d854a60 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

arm64: KVM: enable initialization of a 32bit vcpu 



Wire the init of a 32bit vcpu by allowing 32bit modes in pstate,
and providing sensible defaults out of reset state.

This feature is of course conditioned by the presence of 32bit
capability on the physical CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT
capability.

Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent e82e0305

arch/arm64/include/asm/kvm_host.h

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
#include <kvm/arm_vgic.h>

#include <kvm/arm_arch_timer.h>



#define KVM_VCPU_MAX_FEATURES 1

#define KVM_VCPU_MAX_FEATURES 2



/* We don't currently support large pages. */

#define KVM_HPAGE_GFN_SHIFT(x)	0

arch/arm64/include/uapi/asm/kvm.h

+1 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ struct kvm_regs { 
#define KVM_VGIC_V2_CPU_SIZE		0x2000



#define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */

#define KVM_ARM_VCPU_EL1_32BIT		1 /* CPU running a 32bit VM */



struct kvm_vcpu_init {

	__u32 target;

arch/arm64/kvm/guest.c

+6 −0
Original line number Diff line number Diff line
@@ -99,6 +99,12 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 
	if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {

		u32 mode = (*(u32 *)valp) & COMPAT_PSR_MODE_MASK;

		switch (mode) {

		case COMPAT_PSR_MODE_USR:

		case COMPAT_PSR_MODE_FIQ:

		case COMPAT_PSR_MODE_IRQ:

		case COMPAT_PSR_MODE_SVC:

		case COMPAT_PSR_MODE_ABT:

		case COMPAT_PSR_MODE_UND:

		case PSR_MODE_EL0t:

		case PSR_MODE_EL1t:

		case PSR_MODE_EL1h:

arch/arm64/kvm/reset.c

+25 −1
Original line number Diff line number Diff line
@@ -38,16 +38,32 @@ static const struct kvm_regs default_regs_reset = { 
			PSR_F_BIT | PSR_D_BIT),

};



static const struct kvm_regs default_regs_reset32 = {

	.regs.pstate = (COMPAT_PSR_MODE_SVC | COMPAT_PSR_A_BIT |

			COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),

};



static const struct kvm_irq_level default_vtimer_irq = {

	.irq	= 27,

	.level	= 1,

};



static bool cpu_has_32bit_el1(void)

{

	u64 pfr0;



	pfr0 = read_cpuid(ID_AA64PFR0_EL1);

	return !!(pfr0 & 0x20);

}



int kvm_arch_dev_ioctl_check_extension(long ext)

{

	int r;



	switch (ext) {

	case KVM_CAP_ARM_EL1_32BIT:

		r = cpu_has_32bit_el1();

		break;

	default:

		r = 0;

	}
@@ -70,7 +86,15 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) 


	switch (vcpu->arch.target) {

	default:

		if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {

			if (!cpu_has_32bit_el1())

				return -EINVAL;

			cpu_reset = &default_regs_reset32;

			vcpu->arch.hcr_el2 &= ~HCR_RW;

		} else {

			cpu_reset = &default_regs_reset;

		}



		cpu_vtimer_irq = &default_vtimer_irq;

		break;

	}

include/uapi/linux/kvm.h

+1 −0
Original line number Diff line number Diff line
@@ -666,6 +666,7 @@ struct kvm_ppc_smmu_info { 
#define KVM_CAP_IRQ_MPIC 90

#define KVM_CAP_PPC_RTAS 91

#define KVM_CAP_IRQ_XICS 92

#define KVM_CAP_ARM_EL1_32BIT 93



#ifdef KVM_CAP_IRQ_ROUTING

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