Commit 0d81a3f2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2020-03-13' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "It's a bit quieter, probably not as much as it could be.

  There is on large regression fix in here from Lyude for displayport
  bandwidth calculations, there've been reports of multi-monitor in
  docks not working since -rc1 and this has been tested to fix those.

  Otherwise it's a bunch of i915 (with some GVT fixes), a set of amdgpu
  watermark + bios fixes, and an exynos iommu cleanup fix.

  core:
   - DP MST bandwidth regression fix.

  i915:
   - hard lockup fix
   - GVT fixes
   - 32-bit alignment issue fix
   - timeline wait fixes
   - cacheline_retire and free

  amdgpu:
   - Update the display watermark bounding box for navi14
   - Fix fetching vbios directly from rom on vega20/arcturus
   - Navi and renoir watermark fixes

  exynos:
   - iommu object cleanup fix"

`

* tag 'drm-fixes-2020-03-13' of git://anongit.freedesktop.org/drm/drm:
  drm/dp_mst: Rewrite and fix bandwidth limit checks
  drm/dp_mst: Reprobe path resources in CSN handler
  drm/dp_mst: Use full_pbn instead of available_pbn for bandwidth checks
  drm/dp_mst: Rename drm_dp_mst_is_dp_mst_end_device() to be less redundant
  drm/i915: Defer semaphore priority bumping to a workqueue
  drm/i915/gt: Close race between cacheline_retire and free
  drm/i915/execlists: Enable timeslice on partial virtual engine dequeue
  drm/i915: be more solid in checking the alignment
  drm/i915/gvt: Fix dma-buf display blur issue on CFL
  drm/i915: Return early for await_start on same timeline
  drm/i915: Actually emit the await_start
  drm/amdgpu/powerplay: nv1x, renior copy dcn clock settings of watermark to smu during boot up
  drm/exynos: Fix cleanup of IOMMU related objects
  drm/amdgpu: correct ROM_INDEX/DATA offset for VEGA20
  drm/amd/display: update soc bb for nv14
  drm/i915/gvt: Fix emulated vbt size issue
  drm/i915/gvt: Fix unnecessary schedule timer when no vGPU exits
parents 1b51f694 16b78f05

drivers/gpu/drm/amd/amdgpu/soc15.c

+23 −2
Original line number Diff line number Diff line
@@ -89,6 +89,13 @@ 
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK	0x00010000L

#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK		0x00020000L

#define mmHDP_MEM_POWER_CTRL_BASE_IDX	0



/* for Vega20/arcturus regiter offset change */

#define	mmROM_INDEX_VG20				0x00e4

#define	mmROM_INDEX_VG20_BASE_IDX			0

#define	mmROM_DATA_VG20					0x00e5

#define	mmROM_DATA_VG20_BASE_IDX			0



/*

 * Indirect registers accessor

 */
@@ -309,6 +316,8 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 
{

	u32 *dw_ptr;

	u32 i, length_dw;

	uint32_t rom_index_offset;

	uint32_t rom_data_offset;



	if (bios == NULL)

		return false;
@@ -321,11 +330,23 @@ static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 
	dw_ptr = (u32 *)bios;

	length_dw = ALIGN(length_bytes, 4) / 4;



	switch (adev->asic_type) {

	case CHIP_VEGA20:

	case CHIP_ARCTURUS:

		rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);

		rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);

		break;

	default:

		rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);

		rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);

		break;

	}



	/* set rom index to 0 */

	WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);

	WREG32(rom_index_offset, 0);

	/* read out the rom data */

	for (i = 0; i < length_dw; i++)

		dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));

		dw_ptr[i] = RREG32(rom_data_offset);



	return true;

}

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+114 −0
Original line number Diff line number Diff line
@@ -335,6 +335,117 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 
	.use_urgent_burst_bw = 0

};



struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {

	.clock_limits = {

			{

				.state = 0,

				.dcfclk_mhz = 560.0,

				.fabricclk_mhz = 560.0,

				.dispclk_mhz = 513.0,

				.dppclk_mhz = 513.0,

				.phyclk_mhz = 540.0,

				.socclk_mhz = 560.0,

				.dscclk_mhz = 171.0,

				.dram_speed_mts = 8960.0,

			},

			{

				.state = 1,

				.dcfclk_mhz = 694.0,

				.fabricclk_mhz = 694.0,

				.dispclk_mhz = 642.0,

				.dppclk_mhz = 642.0,

				.phyclk_mhz = 600.0,

				.socclk_mhz = 694.0,

				.dscclk_mhz = 214.0,

				.dram_speed_mts = 11104.0,

			},

			{

				.state = 2,

				.dcfclk_mhz = 875.0,

				.fabricclk_mhz = 875.0,

				.dispclk_mhz = 734.0,

				.dppclk_mhz = 734.0,

				.phyclk_mhz = 810.0,

				.socclk_mhz = 875.0,

				.dscclk_mhz = 245.0,

				.dram_speed_mts = 14000.0,

			},

			{

				.state = 3,

				.dcfclk_mhz = 1000.0,

				.fabricclk_mhz = 1000.0,

				.dispclk_mhz = 1100.0,

				.dppclk_mhz = 1100.0,

				.phyclk_mhz = 810.0,

				.socclk_mhz = 1000.0,

				.dscclk_mhz = 367.0,

				.dram_speed_mts = 16000.0,

			},

			{

				.state = 4,

				.dcfclk_mhz = 1200.0,

				.fabricclk_mhz = 1200.0,

				.dispclk_mhz = 1284.0,

				.dppclk_mhz = 1284.0,

				.phyclk_mhz = 810.0,

				.socclk_mhz = 1200.0,

				.dscclk_mhz = 428.0,

				.dram_speed_mts = 16000.0,

			},

			/*Extra state, no dispclk ramping*/

			{

				.state = 5,

				.dcfclk_mhz = 1200.0,

				.fabricclk_mhz = 1200.0,

				.dispclk_mhz = 1284.0,

				.dppclk_mhz = 1284.0,

				.phyclk_mhz = 810.0,

				.socclk_mhz = 1200.0,

				.dscclk_mhz = 428.0,

				.dram_speed_mts = 16000.0,

			},

		},

	.num_states = 5,

	.sr_exit_time_us = 8.6,

	.sr_enter_plus_exit_time_us = 10.9,

	.urgent_latency_us = 4.0,

	.urgent_latency_pixel_data_only_us = 4.0,

	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,

	.urgent_latency_vm_data_only_us = 4.0,

	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,

	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,

	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,

	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,

	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,

	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,

	.max_avg_sdp_bw_use_normal_percent = 40.0,

	.max_avg_dram_bw_use_normal_percent = 40.0,

	.writeback_latency_us = 12.0,

	.ideal_dram_bw_after_urgent_percent = 40.0,

	.max_request_size_bytes = 256,

	.dram_channel_width_bytes = 2,

	.fabric_datapath_to_dcn_data_return_bytes = 64,

	.dcn_downspread_percent = 0.5,

	.downspread_percent = 0.38,

	.dram_page_open_time_ns = 50.0,

	.dram_rw_turnaround_time_ns = 17.5,

	.dram_return_buffer_per_channel_bytes = 8192,

	.round_trip_ping_latency_dcfclk_cycles = 131,

	.urgent_out_of_order_return_per_channel_bytes = 256,

	.channel_interleave_bytes = 256,

	.num_banks = 8,

	.num_chans = 8,

	.vmm_page_size_bytes = 4096,

	.dram_clock_change_latency_us = 404.0,

	.dummy_pstate_latency_us = 5.0,

	.writeback_dram_clock_change_latency_us = 23.0,

	.return_bus_width_bytes = 64,

	.dispclk_dppclk_vco_speed_mhz = 3850,

	.xfc_bus_transport_time_us = 20,

	.xfc_xbuf_latency_tolerance_us = 4,

	.use_urgent_burst_bw = 0

};



struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };



#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
@@ -3291,6 +3402,9 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st 
static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(

	uint32_t hw_internal_rev)

{

	if (ASICREV_IS_NAVI14_M(hw_internal_rev))

		return &dcn2_0_nv14_soc;



	if (ASICREV_IS_NAVI12_P(hw_internal_rev))

		return &dcn2_0_nv12_soc;

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+5 −2
Original line number Diff line number Diff line
@@ -2006,9 +2006,12 @@ int smu_set_watermarks_for_clock_ranges(struct smu_context *smu, 
			smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&

			smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

		smu_set_watermarks_table(smu, table, clock_ranges);



		if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {

			smu->watermarks_bitmap |= WATERMARKS_EXIST;

			smu->watermarks_bitmap &= ~WATERMARKS_LOADED;

		}

	}



	mutex_unlock(&smu->mutex);

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+13 −9
Original line number Diff line number Diff line
@@ -1062,15 +1062,6 @@ static int navi10_display_config_changed(struct smu_context *smu) 
{

	int ret = 0;



	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

	    !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {

		ret = smu_write_watermarks_table(smu);

		if (ret)

			return ret;



		smu->watermarks_bitmap |= WATERMARKS_LOADED;

	}



	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&

	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
@@ -1493,6 +1484,7 @@ static int navi10_set_watermarks_table(struct smu_context *smu, 
				       *clock_ranges)

{

	int i;

	int ret = 0;

	Watermarks_t *table = watermarks;



	if (!table || !clock_ranges)
@@ -1544,6 +1536,18 @@ static int navi10_set_watermarks_table(struct smu_context *smu, 
				clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;

	}



	smu->watermarks_bitmap |= WATERMARKS_EXIST;



	/* pass data to smu controller */

	if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {

		ret = smu_write_watermarks_table(smu);

		if (ret) {

			pr_err("Failed to update WMTABLE!");

			return ret;

		}

		smu->watermarks_bitmap |= WATERMARKS_LOADED;

	}



	return 0;

}

drivers/gpu/drm/amd/powerplay/renoir_ppt.c

+3 −2
Original line number Diff line number Diff line
@@ -806,9 +806,10 @@ static int renoir_set_watermarks_table( 
				clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;

	}



	smu->watermarks_bitmap |= WATERMARKS_EXIST;



	/* pass data to smu controller */

	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

			!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {

	if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {

		ret = smu_write_watermarks_table(smu);

		if (ret) {

			pr_err("Failed to update WMTABLE!");

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