Commit 0d601f61 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'kirkwood/addr_decode' of... 

Merge branch 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux into late/kirkwood

* 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux

:
  arm: mvebu: add address decoding controller to the DT
  arm: mvebu: add basic address decoding support to Armada 370/XP
  arm: plat-orion: make bridge_virt_base non-const to support DT use case
  arm: plat-orion: introduce PLAT_ORION_LEGACY hidden config option
  arm: plat-orion: use void __iomem pointers for addr-map functions
  arm: plat-orion: use void __iomem pointers for time functions
  arm: plat-orion: use void __iomem pointers for MPP functions
  arm: plat-orion: use void __iomem pointers for UART registration functions
  arm: mach-mvebu: use IOMEM() for base address definitions
  arm: mach-orion5x: use IOMEM() for base address definitions
  arm: mach-mv78xx0: use IOMEM() for base address definitions
  arm: mach-kirkwood: use IOMEM() for base address definitions
  arm: mach-dove: use IOMEM() for base address definitions
  arm: mach-orion5x: use plus instead of or for address definitions
  arm: mach-mv78xx0: use plus instead of or for address definitions
  arm: mach-kirkwood: use plus instead of or for address definitions
  arm: mach-dove: use plus instead of or for address definitions

This branch had quite a few conflicts, in particular with the PCI static
map rework from Rob Herring, and a few other context conflicts due to
changes in Kconfig, etc.

I fixed up conflicts in:
	arch/arm/Kconfig
	arch/arm/mach-dove/common.c
	arch/arm/mach-dove/include/mach/dove.h
	arch/arm/mach-kirkwood/common.c
	arch/arm/mach-kirkwood/include/mach/kirkwood.h
	arch/arm/mach-mv78xx0/common.c
	arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
	arch/arm/mach-orion5x/common.c
	arch/arm/mach-orion5x/include/mach/orion5x.h

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents d7ffa223 5b40baee

arch/arm/Kconfig

+8 −4
Original line number Diff line number Diff line
@@ -540,7 +540,7 @@ config ARCH_DOVE 
	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_CLOCKEVENTS

	select MIGHT_HAVE_PCI

	select PLAT_ORION

	select PLAT_ORION_LEGACY

	select USB_ARCH_HAS_EHCI

	help

	  Support for the Marvell Dove SoC 88AP510
@@ -551,7 +551,7 @@ config ARCH_KIRKWOOD 
	select PCI

	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_CLOCKEVENTS

	select PLAT_ORION

	select PLAT_ORION_LEGACY

	help

	  Support for the following Marvell Kirkwood series SoCs:

	  88F6180, 88F6192 and 88F6281.
@@ -577,7 +577,7 @@ config ARCH_MV78XX0 
	select PCI

	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_CLOCKEVENTS

	select PLAT_ORION

	select PLAT_ORION_LEGACY

	help

	  Support for the following Marvell MV78xx0 series SoCs:

	  MV781x0, MV782x0.
@@ -589,7 +589,7 @@ config ARCH_ORION5X 
	select PCI

	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_CLOCKEVENTS

	select PLAT_ORION

	select PLAT_ORION_LEGACY

	help

	  Support for the following Marvell Orion 5x series SoCs:

	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@ -1146,6 +1146,10 @@ config PLAT_ORION 
	select IRQ_DOMAIN

	select COMMON_CLK



config PLAT_ORION_LEGACY

	bool

	select PLAT_ORION



config PLAT_PXA

	bool

arch/arm/boot/dts/armada-370-xp.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -63,6 +63,11 @@ 
			       reg = <0xd0020300 0x30>;

			       interrupts = <37>, <38>, <39>, <40>;

		};



		addr-decoding@d0020000 {

			compatible = "marvell,armada-addr-decoding-controller";

			reg = <0xd0020000 0x258>;

		};

	};

};

arch/arm/mach-dove/common.c

+2 −2
Original line number Diff line number Diff line
@@ -41,12 +41,12 @@ 
 ****************************************************************************/

static struct map_desc dove_io_desc[] __initdata = {

	{

		.virtual	= DOVE_SB_REGS_VIRT_BASE,

		.virtual	= (unsigned long) DOVE_SB_REGS_VIRT_BASE,

		.pfn		= __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),

		.length		= DOVE_SB_REGS_SIZE,

		.type		= MT_DEVICE,

	}, {

		.virtual	= DOVE_NB_REGS_VIRT_BASE,

		.virtual	= (unsigned long) DOVE_NB_REGS_VIRT_BASE,

		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),

		.length		= DOVE_NB_REGS_SIZE,

		.type		= MT_DEVICE,

arch/arm/mach-dove/include/mach/bridge-regs.h

+8 −8
Original line number Diff line number Diff line
@@ -13,22 +13,22 @@ 


#include <mach/dove.h>



#define CPU_CONFIG		(BRIDGE_VIRT_BASE | 0x0000)

#define CPU_CONFIG		(BRIDGE_VIRT_BASE + 0x0000)



#define CPU_CONTROL		(BRIDGE_VIRT_BASE | 0x0104)

#define CPU_CONTROL		(BRIDGE_VIRT_BASE + 0x0104)

#define  CPU_CTRL_PCIE0_LINK	0x00000001

#define  CPU_RESET		0x00000002

#define  CPU_CTRL_PCIE1_LINK	0x00000008



#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE | 0x0108)

#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)

#define  SOFT_RESET_OUT_EN	0x00000004



#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE | 0x010c)

#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)

#define  SOFT_RESET		0x00000001



#define  BRIDGE_INT_TIMER1_CLR	(~0x0004)



#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0200)

#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)

#define IRQ_CAUSE_LOW_OFF	0x0000

#define IRQ_MASK_LOW_OFF	0x0004

#define FIQ_MASK_LOW_OFF	0x0008
@@ -47,9 +47,9 @@ 
#define ENDPOINT_MASK_HIGH	(IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)

#define PCIE_INTERRUPT_MASK	(IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)



#define POWER_MANAGEMENT	(BRIDGE_VIRT_BASE | 0x011c)

#define POWER_MANAGEMENT	(BRIDGE_VIRT_BASE + 0x011c)



#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0300)

#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)

#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0300)

#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)



#endif

arch/arm/mach-dove/include/mach/dove.h

+63 −63
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ 
 */



#define DOVE_CESA_PHYS_BASE		0xc8000000

#define DOVE_CESA_VIRT_BASE		0xfdb00000

#define DOVE_CESA_VIRT_BASE		IOMEM(0xfdb00000)

#define DOVE_CESA_SIZE			SZ_1M



#define DOVE_PCIE0_MEM_PHYS_BASE	0xe0000000
@@ -38,15 +38,15 @@ 
#define DOVE_BOOTROM_SIZE		SZ_128M



#define DOVE_SCRATCHPAD_PHYS_BASE	0xf0000000

#define DOVE_SCRATCHPAD_VIRT_BASE	0xfdd00000

#define DOVE_SCRATCHPAD_VIRT_BASE	IOMEM(0xfdd00000)

#define DOVE_SCRATCHPAD_SIZE		SZ_1M



#define DOVE_SB_REGS_PHYS_BASE		0xf1000000

#define DOVE_SB_REGS_VIRT_BASE		0xfde00000

#define DOVE_SB_REGS_VIRT_BASE		IOMEM(0xfde00000)

#define DOVE_SB_REGS_SIZE		SZ_8M



#define DOVE_NB_REGS_PHYS_BASE		0xf1800000

#define DOVE_NB_REGS_VIRT_BASE		0xfe600000

#define DOVE_NB_REGS_VIRT_BASE		IOMEM(0xfe600000)

#define DOVE_NB_REGS_SIZE		SZ_8M



#define DOVE_PCIE0_IO_PHYS_BASE		0xf2000000
@@ -62,75 +62,75 @@ 
 */



/* SPI, I2C, UART */

#define DOVE_I2C_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x11000)

#define DOVE_UART0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x12000)

#define DOVE_UART0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x12000)

#define DOVE_UART1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x12100)

#define DOVE_UART1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x12100)

#define DOVE_UART2_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x12200)

#define DOVE_UART2_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x12200)

#define DOVE_UART3_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x12300)

#define DOVE_UART3_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x12300)

#define DOVE_SPI0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x10600)

#define DOVE_SPI1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x14600)

#define DOVE_I2C_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x11000)

#define DOVE_UART0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12000)

#define DOVE_UART0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12000)

#define DOVE_UART1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12100)

#define DOVE_UART1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12100)

#define DOVE_UART2_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12200)

#define DOVE_UART2_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12200)

#define DOVE_UART3_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12300)

#define DOVE_UART3_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12300)

#define DOVE_SPI0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x10600)

#define DOVE_SPI1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x14600)



/* North-South Bridge */

#define BRIDGE_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x20000)

#define BRIDGE_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x20000)

#define BRIDGE_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x20000)

#define BRIDGE_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x20000)



/* Cryptographic Engine */

#define DOVE_CRYPT_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x30000)

#define DOVE_CRYPT_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x30000)



/* PCIe 0 */

#define DOVE_PCIE0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x40000)

#define DOVE_PCIE0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x40000)



/* USB */

#define DOVE_USB0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x50000)

#define DOVE_USB1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x51000)

#define DOVE_USB0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x50000)

#define DOVE_USB1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x51000)



/* XOR 0 Engine */

#define DOVE_XOR0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x60800)

#define DOVE_XOR0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x60800)

#define DOVE_XOR0_HIGH_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x60A00)

#define DOVE_XOR0_HIGH_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x60A00)

#define DOVE_XOR0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60800)

#define DOVE_XOR0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60800)

#define DOVE_XOR0_HIGH_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60A00)

#define DOVE_XOR0_HIGH_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60A00)



/* XOR 1 Engine */

#define DOVE_XOR1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x60900)

#define DOVE_XOR1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x60900)

#define DOVE_XOR1_HIGH_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x60B00)

#define DOVE_XOR1_HIGH_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x60B00)

#define DOVE_XOR1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60900)

#define DOVE_XOR1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60900)

#define DOVE_XOR1_HIGH_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60B00)

#define DOVE_XOR1_HIGH_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60B00)



/* Gigabit Ethernet */

#define DOVE_GE00_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x70000)

#define DOVE_GE00_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x70000)



/* PCIe 1 */

#define DOVE_PCIE1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0x80000)

#define DOVE_PCIE1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x80000)



/* CAFE */

#define DOVE_SDIO0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x92000)

#define DOVE_SDIO1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x90000)

#define DOVE_CAM_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x94000)

#define DOVE_CAFE_WIN_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0x98000)

#define DOVE_SDIO0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x92000)

#define DOVE_SDIO1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x90000)

#define DOVE_CAM_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x94000)

#define DOVE_CAFE_WIN_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x98000)



/* SATA */

#define DOVE_SATA_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0xa0000)

#define DOVE_SATA_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xa0000)



/* I2S/SPDIF */

#define DOVE_AUD0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0xb0000)

#define DOVE_AUD1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0xb4000)

#define DOVE_AUD0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xb0000)

#define DOVE_AUD1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xb4000)



/* NAND Flash Controller */

#define DOVE_NFC_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0xc0000)

#define DOVE_NFC_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xc0000)



/* MPP, GPIO, Reset Sampling */

#define DOVE_MPP_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xd0200)

#define DOVE_MPP_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0200)

#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)

#define DOVE_RESET_SAMPLE_LO	(DOVE_MPP_VIRT_BASE | 0x014)

#define DOVE_RESET_SAMPLE_HI	(DOVE_MPP_VIRT_BASE | 0x018)

#define DOVE_GPIO_LO_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xd0400)

#define DOVE_GPIO_HI_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xd0420)

#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)

#define DOVE_MPP_GENERAL_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xe803c)

#define DOVE_RESET_SAMPLE_LO	(DOVE_MPP_VIRT_BASE + 0x014)

#define DOVE_RESET_SAMPLE_HI	(DOVE_MPP_VIRT_BASE + 0x018)

#define DOVE_GPIO_LO_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0400)

#define DOVE_GPIO_HI_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0420)

#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0xe8400)

#define DOVE_MPP_GENERAL_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe803c)

#define  DOVE_AU1_SPDIFO_GPIO_EN	(1 << 1)

#define  DOVE_NAND_GPIO_EN		(1 << 0)

#define DOVE_MPP_CTRL4_VIRT_BASE	(DOVE_GPIO_LO_VIRT_BASE + 0x40)
@@ -142,44 +142,44 @@ 
#define  DOVE_SD0_GPIO_SEL		(1 << 0)



/* Power Management */

#define DOVE_PMU_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xd0000)

#define DOVE_PMU_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0000)

#define DOVE_PMU_SIG_CTRL	(DOVE_PMU_VIRT_BASE + 0x802c)



/* Real Time Clock */

#define DOVE_RTC_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0xd8500)

#define DOVE_RTC_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xd8500)



/* AC97 */

#define DOVE_AC97_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0xe0000)

#define DOVE_AC97_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xe0000)

#define DOVE_AC97_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xe0000)

#define DOVE_AC97_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe0000)



/* Peripheral DMA */

#define DOVE_PDMA_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0xe4000)

#define DOVE_PDMA_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE | 0xe4000)

#define DOVE_PDMA_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xe4000)

#define DOVE_PDMA_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe4000)



#define DOVE_GLOBAL_CONFIG_1	(DOVE_SB_REGS_VIRT_BASE | 0xe802C)

#define DOVE_GLOBAL_CONFIG_1	(DOVE_SB_REGS_VIRT_BASE + 0xe802C)

#define  DOVE_TWSI_ENABLE_OPTION1	(1 << 7)

#define DOVE_GLOBAL_CONFIG_2	(DOVE_SB_REGS_VIRT_BASE | 0xe8030)

#define DOVE_GLOBAL_CONFIG_2	(DOVE_SB_REGS_VIRT_BASE + 0xe8030)

#define  DOVE_TWSI_ENABLE_OPTION2	(1 << 20)

#define  DOVE_TWSI_ENABLE_OPTION3	(1 << 21)

#define  DOVE_TWSI_OPTION3_GPIO		(1 << 22)

#define DOVE_SSP_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE | 0xec000)

#define DOVE_SSP_CTRL_STATUS_1	(DOVE_SB_REGS_VIRT_BASE | 0xe8034)

#define DOVE_SSP_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xec000)

#define DOVE_SSP_CTRL_STATUS_1	(DOVE_SB_REGS_VIRT_BASE + 0xe8034)

#define  DOVE_SSP_ON_AU1		(1 << 0)

#define  DOVE_SSP_CLOCK_ENABLE		(1 << 1)

#define  DOVE_SSP_BPB_CLOCK_SRC_SSP	(1 << 11)

/* Memory Controller */

#define DOVE_MC_VIRT_BASE	(DOVE_NB_REGS_VIRT_BASE | 0x00000)

#define DOVE_MC_VIRT_BASE	(DOVE_NB_REGS_VIRT_BASE + 0x00000)



/* LCD Controller */

#define DOVE_LCD_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE | 0x10000)

#define DOVE_LCD1_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE | 0x20000)

#define DOVE_LCD2_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE | 0x10000)

#define DOVE_LCD_DCON_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE | 0x30000)

#define DOVE_LCD_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x10000)

#define DOVE_LCD1_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x20000)

#define DOVE_LCD2_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x10000)

#define DOVE_LCD_DCON_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x30000)



/* Graphic Engine */

#define DOVE_GPU_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE | 0x40000)

#define DOVE_GPU_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x40000)



/* Video Engine */

#define DOVE_VPU_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE | 0x400000)

#define DOVE_VPU_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x400000)



#endif

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