Commit 0d2e90f4 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.10-2020-10-09' of... 

Merge tag 'amd-drm-fixes-5.10-2020-10-09' of git://people.freedesktop.org/~agd5f/linux

 into drm-next

amd-drm-fixes-5.10-2020-10-09:

amdgpu:
- Clean up indirect register access
- Navy Flounder fixes
- SMU11 AC/DC interrupt fixes
- GPUVM alignment fix
- Display fixes
- Misc other fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201009222810.4030-1-alexander.deucher@amd.com
parents 2e49520e 9c27bc97

Documentation/gpu/amdgpu.rst

+9 −0
Original line number Diff line number Diff line
@@ -70,6 +70,15 @@ Interrupt Handling 
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

   :internal:



IP Blocks

------------------



.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h

   :doc: IP Blocks



.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h

   :identifiers: amd_ip_block_type amd_ip_funcs



AMDGPU XGMI Support

===================

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+29 −11
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ 
#include "amdgpu_mes.h"

#include "amdgpu_umc.h"

#include "amdgpu_mmhub.h"

#include "amdgpu_gfxhub.h"

#include "amdgpu_df.h"



#define MAX_GPU_INSTANCE		16
@@ -881,6 +882,9 @@ struct amdgpu_device { 
	/* mmhub */

	struct amdgpu_mmhub		mmhub;



	/* gfxhub */

	struct amdgpu_gfxhub		gfxhub;



	/* gfx */

	struct amdgpu_gfx		gfx;
@@ -1016,18 +1020,32 @@ int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 


void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,

			       uint32_t *buf, size_t size, bool write);

uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,

			uint32_t acc_flags);

void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

		    uint32_t acc_flags);

void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,

			    uint32_t reg, uint32_t acc_flags);

void amdgpu_device_wreg(struct amdgpu_device *adev,

			uint32_t reg, uint32_t v,

			uint32_t acc_flags);

void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,

			     uint32_t reg, uint32_t v);

void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);

uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);



u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);

void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);



u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,

				u32 pcie_index, u32 pcie_data,

				u32 reg_addr);

u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,

				  u32 pcie_index, u32 pcie_data,

				  u32 reg_addr);

void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,

				 u32 pcie_index, u32 pcie_data,

				 u32 reg_addr, u32 reg_data);

void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,

				   u32 pcie_index, u32 pcie_data,

				   u32 reg_addr, u64 reg_data);



bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);

bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
@@ -1038,8 +1056,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
 */

#define AMDGPU_REGS_NO_KIQ    (1<<1)



#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)

#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)



#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))

#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
@@ -1047,9 +1065,9 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))

#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))



#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))

#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)

#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))

#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)

#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
@@ -1095,7 +1113,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
		WREG32_SMC(_Reg, tmp);                          \

	} while (0)



#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))

#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))

#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))

#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))

drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c

+1 −1
Original line number Diff line number Diff line
@@ -806,8 +806,8 @@ int amdgpu_acpi_init(struct amdgpu_device *adev) 
	}

	adev->atif = atif;



	if (atif->notifications.brightness_change) {

#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

	if (atif->notifications.brightness_change) {

		if (amdgpu_device_has_dc_support(adev)) {

#if defined(CONFIG_DRM_AMD_DC)

			struct amdgpu_display_manager *dm = &adev->dm;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+17 −1
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ 
 */

uint64_t amdgpu_amdkfd_total_mem_size;



static bool kfd_initialized;



int amdgpu_amdkfd_init(void)

{

	struct sysinfo si;
@@ -51,19 +53,26 @@ int amdgpu_amdkfd_init(void) 
#else

	ret = -ENOENT;

#endif

	kfd_initialized = !ret;



	return ret;

}



void amdgpu_amdkfd_fini(void)

{

	if (kfd_initialized) {

		kgd2kfd_exit();

		kfd_initialized = false;

	}

}



void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)

{

	bool vf = amdgpu_sriov_vf(adev);



	if (!kfd_initialized)

		return;



	adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,

				      adev->pdev, adev->asic_type, vf);
@@ -572,6 +581,13 @@ uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd) 
	return adev->rev_id;

}



int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;



	return adev->gmc.noretry;

}



int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,

				uint32_t vmid, uint64_t gpu_addr,

				uint32_t *ib_cmd, uint32_t ib_len)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h

+1 −0
Original line number Diff line number Diff line
@@ -181,6 +181,7 @@ uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd); 
uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd);

uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);

uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd);

int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd);

uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);



/* Read user wptr from a specified user address space with page fault

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