Commit 0d2602d7 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: cpg-mssr: Add support for fixed rate clocks 



Add support for defining fixed rate clocks, to be used for on-chip
oscillators.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 3a251270

drivers/clk/renesas/renesas-cpg-mssr.c

+5 −0
Original line number Diff line number Diff line
@@ -313,6 +313,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 
		}

		break;



	case CLK_TYPE_FR:

		clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,

					      core->mult);

		break;



	default:

		if (info->cpg_clk_register)

			clk = info->cpg_clk_register(dev, core, info,

drivers/clk/renesas/renesas-cpg-mssr.h

+3 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ enum clk_types { 
	CLK_TYPE_FF,		/* Fixed Factor Clock */

	CLK_TYPE_DIV6P1,	/* DIV6 Clock with 1 parent clock */

	CLK_TYPE_DIV6_RO,	/* DIV6 Clock read only with extra divisor */

	CLK_TYPE_FR,		/* Fixed Rate Clock */



	/* Custom definitions start here */

	CLK_TYPE_CUSTOM,
@@ -56,6 +57,8 @@ enum clk_types { 
	DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)

#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div)	\

	DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)

#define DEF_RATE(_name, _id, _rate)	\

	DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)



    /*

     * Definitions of Module Clocks

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