Commit 0d10d17b authored by 周琰杰 (Zhou Yanjie)'s avatar 周琰杰 (Zhou Yanjie) Committed by Thomas Bogendoerfer
Browse files

MIPS: X2000: Add X2000 system type. 



1.Add "PRID_COMP_INGENIC_13" and "PRID_IMP_XBURST2" for X2000.
2.Add X2000 system type for cat /proc/cpuinfo to give out X2000.

Signed-off-by: default avatar周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent e8b9fc10

arch/mips/include/asm/bootinfo.h

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ enum ingenic_machine_type { 
	MACH_INGENIC_JZ4780,

	MACH_INGENIC_X1000,

	MACH_INGENIC_X1830,

	MACH_INGENIC_X2000,

};



extern char *system_type;

arch/mips/include/asm/cpu.h

+4 −2
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
#define PRID_COMP_NETLOGIC	0x0c0000

#define PRID_COMP_CAVIUM	0x0d0000

#define PRID_COMP_LOONGSON	0x140000

#define PRID_COMP_INGENIC_13	0x130000	/* X2000 */

#define PRID_COMP_INGENIC_D0	0xd00000	/* JZ4740, JZ4750, X1830 */

#define PRID_COMP_INGENIC_D1	0xd10000	/* JZ4770, JZ4775, X1000 */

#define PRID_COMP_INGENIC_E1	0xe10000	/* JZ4780 */
@@ -185,8 +186,9 @@ 
 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*

 */



#define PRID_IMP_XBURST_REV1	0x0200	/* XBurst with MXU SIMD ISA		*/

#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst with MXU2 SIMD ISA	*/

#define PRID_IMP_XBURST_REV1	0x0200	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA	*/

#define PRID_IMP_XBURST_REV2	0x0100	/* XBurst®1 with MXU2.0 SIMD ISA		*/

#define PRID_IMP_XBURST2		0x2000	/* XBurst®2 with MXU2.1 SIMD ISA		*/



/*

 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC

arch/mips/jz4740/setup.c

+4 −0
Original line number Diff line number Diff line
@@ -49,6 +49,8 @@ static void __init jz4740_detect_mem(void) 


static unsigned long __init get_board_mach_type(const void *fdt)

{

	if (!fdt_node_check_compatible(fdt, 0, "ingenic,x2000"))

		return MACH_INGENIC_X2000;

	if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1830"))

		return MACH_INGENIC_X1830;

	if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1000"))
@@ -93,6 +95,8 @@ void __init device_tree_init(void) 
const char *get_system_type(void)

{

	switch (mips_machtype) {

	case MACH_INGENIC_X2000:

		return "X2000";

	case MACH_INGENIC_X1830:

		return "X1830";

	case MACH_INGENIC_X1000:

arch/mips/kernel/cpu-probe.c

+11 −0
Original line number Diff line number Diff line
@@ -2110,6 +2110,8 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 
	BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);



	switch (c->processor_id & PRID_IMP_MASK) {



	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */

	case PRID_IMP_XBURST_REV1:



		/*
@@ -2148,12 +2150,20 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 
			break;

		}

		fallthrough;



	/* XBurst®1 with MXU2.0 SIMD ISA */

	case PRID_IMP_XBURST_REV2:

		c->cputype = CPU_XBURST;

		c->writecombine = _CACHE_UNCACHED_ACCELERATED;

		__cpu_name[cpu] = "Ingenic XBurst";

		break;



	/* XBurst®2 with MXU2.1 SIMD ISA */

	case PRID_IMP_XBURST2:

		c->cputype = CPU_XBURST;

		__cpu_name[cpu] = "Ingenic XBurst II";

		break;



	default:

		panic("Unknown Ingenic Processor ID!");

		break;
@@ -2299,6 +2309,7 @@ void cpu_probe(void) 
	case PRID_COMP_LOONGSON:

		cpu_probe_loongson(c, cpu);

		break;

	case PRID_COMP_INGENIC_13:

	case PRID_COMP_INGENIC_D0:

	case PRID_COMP_INGENIC_D1:

	case PRID_COMP_INGENIC_E1:

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