Commit 0cef5dd4 authored by Taniya Das's avatar Taniya Das Committed by Andy Gross
Browse files

arm64: dts: sdm845: Add lpasscc node 



This adds the low pass audio clock controller node to sdm845 based on
the example in the bindings.

Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
[bjorn: Disabled lpasscc node, as it's normally protected]
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>

Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 05556681

arch/arm64/boot/dts/qcom/sdm845-mtp.dts

+3 −1
Original line number Diff line number Diff line
@@ -347,7 +347,9 @@ 
&gcc {

	protected-clocks = <GCC_QSPI_CORE_CLK>,

			   <GCC_QSPI_CORE_CLK_SRC>,

			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;

			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,

			   <GCC_LPASS_Q6_AXI_CLK>,

			   <GCC_LPASS_SWAY_CLK>;

};



&i2c10 {

arch/arm64/boot/dts/qcom/sdm845.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <dt-bindings/clock/qcom,dispcc-sdm845.h>

#include <dt-bindings/clock/qcom,gcc-sdm845.h>

#include <dt-bindings/clock/qcom,lpass-sdm845.h>

#include <dt-bindings/clock/qcom,gpucc-sdm845.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,videocc-sdm845.h>
@@ -2008,6 +2009,14 @@ 
				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;

		};



		lpasscc: clock-controller@17014000 {

			compatible = "qcom,sdm845-lpasscc";

			reg = <0x17014000 0x1f004>, <0x17300000 0x200>;

			reg-names = "cc", "qdsp6ss";

			#clock-cells = <1>;

			status = "disabled";

		};



		apss_shared: mailbox@17990000 {

			compatible = "qcom,sdm845-apss-shared";

			reg = <0x17990000 0x1000>;

CRA Git | Maintained and supported by SUSTech CRA and CCSE