Commit 0ce7b4a7 authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

ARM: dts: imx6sl: correct PWM ipg clock source 



From i.MX6SL Reference Manual, the PWMx's ipg clock
for registers access is from perclk, correct them.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Acked-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 5ddb78d6

arch/arm/boot/dts/imx6sl.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -338,7 +338,7 @@ 
				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";

				reg = <0x02080000 0x4000>;

				interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6SL_CLK_PWM1>,

				clocks = <&clks IMX6SL_CLK_PERCLK>,

					 <&clks IMX6SL_CLK_PWM1>;

				clock-names = "ipg", "per";

			};
@@ -348,7 +348,7 @@ 
				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";

				reg = <0x02084000 0x4000>;

				interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6SL_CLK_PWM2>,

				clocks = <&clks IMX6SL_CLK_PERCLK>,

					 <&clks IMX6SL_CLK_PWM2>;

				clock-names = "ipg", "per";

			};
@@ -358,7 +358,7 @@ 
				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";

				reg = <0x02088000 0x4000>;

				interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6SL_CLK_PWM3>,

				clocks = <&clks IMX6SL_CLK_PERCLK>,

					 <&clks IMX6SL_CLK_PWM3>;

				clock-names = "ipg", "per";

			};
@@ -368,7 +368,7 @@ 
				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";

				reg = <0x0208c000 0x4000>;

				interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clks IMX6SL_CLK_PWM4>,

				clocks = <&clks IMX6SL_CLK_PERCLK>,

					 <&clks IMX6SL_CLK_PWM4>;

				clock-names = "ipg", "per";

			};

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