Commit 0ce339a9 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'arm64/common-esr-macros' of git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux 

ESR_ELx definitions clean-up from Mark Rutland.

* 'arm64/common-esr-macros' of git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux:
  arm64: kvm: decode ESR_ELx.EC when reporting exceptions
  arm64: kvm: remove ESR_EL2_* macros
  arm64: remove ESR_EL1_* macros
  arm64: kvm: move to ESR_ELx macros
  arm64: decode ESR_ELx.EC when reporting exceptions
  arm64: move to ESR_ELx macros
  arm64: introduce common ESR_ELx_* definitions
parents 5d425c18 056bb5f5

arch/arm64/include/asm/esr.h

+83 −34
Original line number Diff line number Diff line
@@ -18,40 +18,89 @@ 
#ifndef __ASM_ESR_H

#define __ASM_ESR_H



#define ESR_EL1_WRITE		(1 << 6)

#define ESR_EL1_CM		(1 << 8)

#define ESR_EL1_IL		(1 << 25)

#define ESR_ELx_EC_UNKNOWN	(0x00)

#define ESR_ELx_EC_WFx		(0x01)

/* Unallocated EC: 0x02 */

#define ESR_ELx_EC_CP15_32	(0x03)

#define ESR_ELx_EC_CP15_64	(0x04)

#define ESR_ELx_EC_CP14_MR	(0x05)

#define ESR_ELx_EC_CP14_LS	(0x06)

#define ESR_ELx_EC_FP_ASIMD	(0x07)

#define ESR_ELx_EC_CP10_ID	(0x08)

/* Unallocated EC: 0x09 - 0x0B */

#define ESR_ELx_EC_CP14_64	(0x0C)

/* Unallocated EC: 0x0d */

#define ESR_ELx_EC_ILL		(0x0E)

/* Unallocated EC: 0x0F - 0x10 */

#define ESR_ELx_EC_SVC32	(0x11)

#define ESR_ELx_EC_HVC32	(0x12)

#define ESR_ELx_EC_SMC32	(0x13)

/* Unallocated EC: 0x14 */

#define ESR_ELx_EC_SVC64	(0x15)

#define ESR_ELx_EC_HVC64	(0x16)

#define ESR_ELx_EC_SMC64	(0x17)

#define ESR_ELx_EC_SYS64	(0x18)

/* Unallocated EC: 0x19 - 0x1E */

#define ESR_ELx_EC_IMP_DEF	(0x1f)

#define ESR_ELx_EC_IABT_LOW	(0x20)

#define ESR_ELx_EC_IABT_CUR	(0x21)

#define ESR_ELx_EC_PC_ALIGN	(0x22)

/* Unallocated EC: 0x23 */

#define ESR_ELx_EC_DABT_LOW	(0x24)

#define ESR_ELx_EC_DABT_CUR	(0x25)

#define ESR_ELx_EC_SP_ALIGN	(0x26)

/* Unallocated EC: 0x27 */

#define ESR_ELx_EC_FP_EXC32	(0x28)

/* Unallocated EC: 0x29 - 0x2B */

#define ESR_ELx_EC_FP_EXC64	(0x2C)

/* Unallocated EC: 0x2D - 0x2E */

#define ESR_ELx_EC_SERROR	(0x2F)

#define ESR_ELx_EC_BREAKPT_LOW	(0x30)

#define ESR_ELx_EC_BREAKPT_CUR	(0x31)

#define ESR_ELx_EC_SOFTSTP_LOW	(0x32)

#define ESR_ELx_EC_SOFTSTP_CUR	(0x33)

#define ESR_ELx_EC_WATCHPT_LOW	(0x34)

#define ESR_ELx_EC_WATCHPT_CUR	(0x35)

/* Unallocated EC: 0x36 - 0x37 */

#define ESR_ELx_EC_BKPT32	(0x38)

/* Unallocated EC: 0x39 */

#define ESR_ELx_EC_VECTOR32	(0x3A)

/* Unallocted EC: 0x3B */

#define ESR_ELx_EC_BRK64	(0x3C)

/* Unallocated EC: 0x3D - 0x3F */

#define ESR_ELx_EC_MAX		(0x3F)



#define ESR_EL1_EC_SHIFT	(26)

#define ESR_EL1_EC_UNKNOWN	(0x00)

#define ESR_EL1_EC_WFI		(0x01)

#define ESR_EL1_EC_CP15_32	(0x03)

#define ESR_EL1_EC_CP15_64	(0x04)

#define ESR_EL1_EC_CP14_MR	(0x05)

#define ESR_EL1_EC_CP14_LS	(0x06)

#define ESR_EL1_EC_FP_ASIMD	(0x07)

#define ESR_EL1_EC_CP10_ID	(0x08)

#define ESR_EL1_EC_CP14_64	(0x0C)

#define ESR_EL1_EC_ILL_ISS	(0x0E)

#define ESR_EL1_EC_SVC32	(0x11)

#define ESR_EL1_EC_SVC64	(0x15)

#define ESR_EL1_EC_SYS64	(0x18)

#define ESR_EL1_EC_IABT_EL0	(0x20)

#define ESR_EL1_EC_IABT_EL1	(0x21)

#define ESR_EL1_EC_PC_ALIGN	(0x22)

#define ESR_EL1_EC_DABT_EL0	(0x24)

#define ESR_EL1_EC_DABT_EL1	(0x25)

#define ESR_EL1_EC_SP_ALIGN	(0x26)

#define ESR_EL1_EC_FP_EXC32	(0x28)

#define ESR_EL1_EC_FP_EXC64	(0x2C)

#define ESR_EL1_EC_SERROR	(0x2F)

#define ESR_EL1_EC_BREAKPT_EL0	(0x30)

#define ESR_EL1_EC_BREAKPT_EL1	(0x31)

#define ESR_EL1_EC_SOFTSTP_EL0	(0x32)

#define ESR_EL1_EC_SOFTSTP_EL1	(0x33)

#define ESR_EL1_EC_WATCHPT_EL0	(0x34)

#define ESR_EL1_EC_WATCHPT_EL1	(0x35)

#define ESR_EL1_EC_BKPT32	(0x38)

#define ESR_EL1_EC_BRK64	(0x3C)

#define ESR_ELx_EC_SHIFT	(26)

#define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)



#define ESR_ELx_IL		(UL(1) << 25)

#define ESR_ELx_ISS_MASK	(ESR_ELx_IL - 1)

#define ESR_ELx_ISV		(UL(1) << 24)

#define ESR_ELx_SAS_SHIFT	(22)

#define ESR_ELx_SAS		(UL(3) << ESR_ELx_SAS_SHIFT)

#define ESR_ELx_SSE		(UL(1) << 21)

#define ESR_ELx_SRT_SHIFT	(16)

#define ESR_ELx_SRT_MASK	(UL(0x1F) << ESR_ELx_SRT_SHIFT)

#define ESR_ELx_SF 		(UL(1) << 15)

#define ESR_ELx_AR 		(UL(1) << 14)

#define ESR_ELx_EA 		(UL(1) << 9)

#define ESR_ELx_CM 		(UL(1) << 8)

#define ESR_ELx_S1PTW 		(UL(1) << 7)

#define ESR_ELx_WNR		(UL(1) << 6)

#define ESR_ELx_FSC		(0x3F)

#define ESR_ELx_FSC_TYPE	(0x3C)

#define ESR_ELx_FSC_EXTABT	(0x10)

#define ESR_ELx_FSC_FAULT	(0x04)

#define ESR_ELx_FSC_PERM	(0x0C)

#define ESR_ELx_CV		(UL(1) << 24)

#define ESR_ELx_COND_SHIFT	(20)

#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)

#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)



#ifndef __ASSEMBLY__

#include <asm/types.h>



const char *esr_get_class_string(u32 esr);

#endif /* __ASSEMBLY */



#endif /* __ASM_ESR_H */

arch/arm64/include/asm/kvm_arm.h

+4 −69
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#ifndef __ARM64_KVM_ARM_H__

#define __ARM64_KVM_ARM_H__



#include <asm/esr.h>

#include <asm/memory.h>

#include <asm/types.h>
@@ -184,77 +185,11 @@ 
#define MDCR_EL2_TPMCR		(1 << 5)

#define MDCR_EL2_HPMN_MASK	(0x1F)



/* Exception Syndrome Register (ESR) bits */

#define ESR_EL2_EC_SHIFT	(26)

#define ESR_EL2_EC		(UL(0x3f) << ESR_EL2_EC_SHIFT)

#define ESR_EL2_IL		(UL(1) << 25)

#define ESR_EL2_ISS		(ESR_EL2_IL - 1)

#define ESR_EL2_ISV_SHIFT	(24)

#define ESR_EL2_ISV		(UL(1) << ESR_EL2_ISV_SHIFT)

#define ESR_EL2_SAS_SHIFT	(22)

#define ESR_EL2_SAS		(UL(3) << ESR_EL2_SAS_SHIFT)

#define ESR_EL2_SSE		(1 << 21)

#define ESR_EL2_SRT_SHIFT	(16)

#define ESR_EL2_SRT_MASK	(0x1f << ESR_EL2_SRT_SHIFT)

#define ESR_EL2_SF 		(1 << 15)

#define ESR_EL2_AR 		(1 << 14)

#define ESR_EL2_EA 		(1 << 9)

#define ESR_EL2_CM 		(1 << 8)

#define ESR_EL2_S1PTW 		(1 << 7)

#define ESR_EL2_WNR		(1 << 6)

#define ESR_EL2_FSC		(0x3f)

#define ESR_EL2_FSC_TYPE	(0x3c)



#define ESR_EL2_CV_SHIFT	(24)

#define ESR_EL2_CV		(UL(1) << ESR_EL2_CV_SHIFT)

#define ESR_EL2_COND_SHIFT	(20)

#define ESR_EL2_COND		(UL(0xf) << ESR_EL2_COND_SHIFT)





#define FSC_FAULT	(0x04)

#define FSC_PERM	(0x0c)

/* For compatibility with fault code shared with 32-bit */

#define FSC_FAULT	ESR_ELx_FSC_FAULT

#define FSC_PERM	ESR_ELx_FSC_PERM



/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */

#define HPFAR_MASK	(~UL(0xf))



#define ESR_EL2_EC_UNKNOWN	(0x00)

#define ESR_EL2_EC_WFI		(0x01)

#define ESR_EL2_EC_CP15_32	(0x03)

#define ESR_EL2_EC_CP15_64	(0x04)

#define ESR_EL2_EC_CP14_MR	(0x05)

#define ESR_EL2_EC_CP14_LS	(0x06)

#define ESR_EL2_EC_FP_ASIMD	(0x07)

#define ESR_EL2_EC_CP10_ID	(0x08)

#define ESR_EL2_EC_CP14_64	(0x0C)

#define ESR_EL2_EC_ILL_ISS	(0x0E)

#define ESR_EL2_EC_SVC32	(0x11)

#define ESR_EL2_EC_HVC32	(0x12)

#define ESR_EL2_EC_SMC32	(0x13)

#define ESR_EL2_EC_SVC64	(0x15)

#define ESR_EL2_EC_HVC64	(0x16)

#define ESR_EL2_EC_SMC64	(0x17)

#define ESR_EL2_EC_SYS64	(0x18)

#define ESR_EL2_EC_IABT		(0x20)

#define ESR_EL2_EC_IABT_HYP	(0x21)

#define ESR_EL2_EC_PC_ALIGN	(0x22)

#define ESR_EL2_EC_DABT		(0x24)

#define ESR_EL2_EC_DABT_HYP	(0x25)

#define ESR_EL2_EC_SP_ALIGN	(0x26)

#define ESR_EL2_EC_FP_EXC32	(0x28)

#define ESR_EL2_EC_FP_EXC64	(0x2C)

#define ESR_EL2_EC_SERROR	(0x2F)

#define ESR_EL2_EC_BREAKPT	(0x30)

#define ESR_EL2_EC_BREAKPT_HYP	(0x31)

#define ESR_EL2_EC_SOFTSTP	(0x32)

#define ESR_EL2_EC_SOFTSTP_HYP	(0x33)

#define ESR_EL2_EC_WATCHPT	(0x34)

#define ESR_EL2_EC_WATCHPT_HYP	(0x35)

#define ESR_EL2_EC_BKPT32	(0x38)

#define ESR_EL2_EC_VECTOR32	(0x3A)

#define ESR_EL2_EC_BRK64	(0x3C)



#define ESR_EL2_EC_xABT_xFSR_EXTABT	0x10



#define ESR_EL2_EC_WFI_ISS_WFE	(1 << 0)



#endif /* __ARM64_KVM_ARM_H__ */

arch/arm64/include/asm/kvm_emulate.h

+15 −13
Original line number Diff line number Diff line
@@ -23,8 +23,10 @@ 
#define __ARM64_KVM_EMULATE_H__



#include <linux/kvm_host.h>

#include <asm/kvm_asm.h>



#include <asm/esr.h>

#include <asm/kvm_arm.h>

#include <asm/kvm_asm.h>

#include <asm/kvm_mmio.h>

#include <asm/ptrace.h>
@@ -128,63 +130,63 @@ static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu) 


static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_ISV);

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);

}



static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_WNR);

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR);

}



static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SSE);

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);

}



static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)

{

	return (kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SRT_MASK) >> ESR_EL2_SRT_SHIFT;

	return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;

}



static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_EA);

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_EA);

}



static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_S1PTW);

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);

}



static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)

{

	return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SAS) >> ESR_EL2_SAS_SHIFT);

	return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);

}



/* This one is not specific to Data Abort */

static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)

{

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_IL);

	return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);

}



static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) >> ESR_EL2_EC_SHIFT;

	return kvm_vcpu_get_hsr(vcpu) >> ESR_ELx_EC_SHIFT;

}



static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_trap_get_class(vcpu) == ESR_EL2_EC_IABT;

	return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;

}



static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & ESR_EL2_FSC;

	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;

}



static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & ESR_EL2_FSC_TYPE;

	return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;

}



static inline unsigned long kvm_vcpu_get_mpidr(struct kvm_vcpu *vcpu)

arch/arm64/kernel/entry.S

+32 −32
Original line number Diff line number Diff line
@@ -269,18 +269,18 @@ ENDPROC(el1_error_invalid) 
el1_sync:

	kernel_entry 1

	mrs	x1, esr_el1			// read the syndrome register

	lsr	x24, x1, #ESR_EL1_EC_SHIFT	// exception class

	cmp	x24, #ESR_EL1_EC_DABT_EL1	// data abort in EL1

	lsr	x24, x1, #ESR_ELx_EC_SHIFT	// exception class

	cmp	x24, #ESR_ELx_EC_DABT_CUR	// data abort in EL1

	b.eq	el1_da

	cmp	x24, #ESR_EL1_EC_SYS64		// configurable trap

	cmp	x24, #ESR_ELx_EC_SYS64		// configurable trap

	b.eq	el1_undef

	cmp	x24, #ESR_EL1_EC_SP_ALIGN	// stack alignment exception

	cmp	x24, #ESR_ELx_EC_SP_ALIGN	// stack alignment exception

	b.eq	el1_sp_pc

	cmp	x24, #ESR_EL1_EC_PC_ALIGN	// pc alignment exception

	cmp	x24, #ESR_ELx_EC_PC_ALIGN	// pc alignment exception

	b.eq	el1_sp_pc

	cmp	x24, #ESR_EL1_EC_UNKNOWN	// unknown exception in EL1

	cmp	x24, #ESR_ELx_EC_UNKNOWN	// unknown exception in EL1

	b.eq	el1_undef

	cmp	x24, #ESR_EL1_EC_BREAKPT_EL1	// debug exception in EL1

	cmp	x24, #ESR_ELx_EC_BREAKPT_CUR	// debug exception in EL1

	b.ge	el1_dbg

	b	el1_inv

el1_da:
@@ -318,7 +318,7 @@ el1_dbg: 
	/*

	 * Debug exception handling

	 */

	cmp	x24, #ESR_EL1_EC_BRK64		// if BRK64

	cmp	x24, #ESR_ELx_EC_BRK64		// if BRK64

	cinc	x24, x24, eq			// set bit '0'

	tbz	x24, #0, el1_inv		// EL1 only

	mrs	x0, far_el1
@@ -375,26 +375,26 @@ el1_preempt: 
el0_sync:

	kernel_entry 0

	mrs	x25, esr_el1			// read the syndrome register

	lsr	x24, x25, #ESR_EL1_EC_SHIFT	// exception class

	cmp	x24, #ESR_EL1_EC_SVC64		// SVC in 64-bit state

	lsr	x24, x25, #ESR_ELx_EC_SHIFT	// exception class

	cmp	x24, #ESR_ELx_EC_SVC64		// SVC in 64-bit state

	b.eq	el0_svc

	cmp	x24, #ESR_EL1_EC_DABT_EL0	// data abort in EL0

	cmp	x24, #ESR_ELx_EC_DABT_LOW	// data abort in EL0

	b.eq	el0_da

	cmp	x24, #ESR_EL1_EC_IABT_EL0	// instruction abort in EL0

	cmp	x24, #ESR_ELx_EC_IABT_LOW	// instruction abort in EL0

	b.eq	el0_ia

	cmp	x24, #ESR_EL1_EC_FP_ASIMD	// FP/ASIMD access

	cmp	x24, #ESR_ELx_EC_FP_ASIMD	// FP/ASIMD access

	b.eq	el0_fpsimd_acc

	cmp	x24, #ESR_EL1_EC_FP_EXC64	// FP/ASIMD exception

	cmp	x24, #ESR_ELx_EC_FP_EXC64	// FP/ASIMD exception

	b.eq	el0_fpsimd_exc

	cmp	x24, #ESR_EL1_EC_SYS64		// configurable trap

	cmp	x24, #ESR_ELx_EC_SYS64		// configurable trap

	b.eq	el0_undef

	cmp	x24, #ESR_EL1_EC_SP_ALIGN	// stack alignment exception

	cmp	x24, #ESR_ELx_EC_SP_ALIGN	// stack alignment exception

	b.eq	el0_sp_pc

	cmp	x24, #ESR_EL1_EC_PC_ALIGN	// pc alignment exception

	cmp	x24, #ESR_ELx_EC_PC_ALIGN	// pc alignment exception

	b.eq	el0_sp_pc

	cmp	x24, #ESR_EL1_EC_UNKNOWN	// unknown exception in EL0

	cmp	x24, #ESR_ELx_EC_UNKNOWN	// unknown exception in EL0

	b.eq	el0_undef

	cmp	x24, #ESR_EL1_EC_BREAKPT_EL0	// debug exception in EL0

	cmp	x24, #ESR_ELx_EC_BREAKPT_LOW	// debug exception in EL0

	b.ge	el0_dbg

	b	el0_inv
@@ -403,30 +403,30 @@ el0_sync: 
el0_sync_compat:

	kernel_entry 0, 32

	mrs	x25, esr_el1			// read the syndrome register

	lsr	x24, x25, #ESR_EL1_EC_SHIFT	// exception class

	cmp	x24, #ESR_EL1_EC_SVC32		// SVC in 32-bit state

	lsr	x24, x25, #ESR_ELx_EC_SHIFT	// exception class

	cmp	x24, #ESR_ELx_EC_SVC32		// SVC in 32-bit state

	b.eq	el0_svc_compat

	cmp	x24, #ESR_EL1_EC_DABT_EL0	// data abort in EL0

	cmp	x24, #ESR_ELx_EC_DABT_LOW	// data abort in EL0

	b.eq	el0_da

	cmp	x24, #ESR_EL1_EC_IABT_EL0	// instruction abort in EL0

	cmp	x24, #ESR_ELx_EC_IABT_LOW	// instruction abort in EL0

	b.eq	el0_ia

	cmp	x24, #ESR_EL1_EC_FP_ASIMD	// FP/ASIMD access

	cmp	x24, #ESR_ELx_EC_FP_ASIMD	// FP/ASIMD access

	b.eq	el0_fpsimd_acc

	cmp	x24, #ESR_EL1_EC_FP_EXC32	// FP/ASIMD exception

	cmp	x24, #ESR_ELx_EC_FP_EXC32	// FP/ASIMD exception

	b.eq	el0_fpsimd_exc

	cmp	x24, #ESR_EL1_EC_UNKNOWN	// unknown exception in EL0

	cmp	x24, #ESR_ELx_EC_UNKNOWN	// unknown exception in EL0

	b.eq	el0_undef

	cmp	x24, #ESR_EL1_EC_CP15_32	// CP15 MRC/MCR trap

	cmp	x24, #ESR_ELx_EC_CP15_32	// CP15 MRC/MCR trap

	b.eq	el0_undef

	cmp	x24, #ESR_EL1_EC_CP15_64	// CP15 MRRC/MCRR trap

	cmp	x24, #ESR_ELx_EC_CP15_64	// CP15 MRRC/MCRR trap

	b.eq	el0_undef

	cmp	x24, #ESR_EL1_EC_CP14_MR	// CP14 MRC/MCR trap

	cmp	x24, #ESR_ELx_EC_CP14_MR	// CP14 MRC/MCR trap

	b.eq	el0_undef

	cmp	x24, #ESR_EL1_EC_CP14_LS	// CP14 LDC/STC trap

	cmp	x24, #ESR_ELx_EC_CP14_LS	// CP14 LDC/STC trap

	b.eq	el0_undef

	cmp	x24, #ESR_EL1_EC_CP14_64	// CP14 MRRC/MCRR trap

	cmp	x24, #ESR_ELx_EC_CP14_64	// CP14 MRRC/MCRR trap

	b.eq	el0_undef

	cmp	x24, #ESR_EL1_EC_BREAKPT_EL0	// debug exception in EL0

	cmp	x24, #ESR_ELx_EC_BREAKPT_LOW	// debug exception in EL0

	b.ge	el0_dbg

	b	el0_inv

el0_svc_compat:

arch/arm64/kernel/signal32.c

+1 −1
Original line number Diff line number Diff line
@@ -501,7 +501,7 @@ static int compat_setup_sigframe(struct compat_sigframe __user *sf, 


	__put_user_error((compat_ulong_t)0, &sf->uc.uc_mcontext.trap_no, err);

	/* set the compat FSR WnR */

	__put_user_error(!!(current->thread.fault_code & ESR_EL1_WRITE) <<

	__put_user_error(!!(current->thread.fault_code & ESR_ELx_WNR) <<

			 FSR_WRITE_SHIFT, &sf->uc.uc_mcontext.error_code, err);

	__put_user_error(current->thread.fault_address, &sf->uc.uc_mcontext.fault_address, err);

	__put_user_error(set->sig[0], &sf->uc.uc_mcontext.oldmask, err);

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