Commit 0ccbc7cd authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher
Browse files

drm/amdkfd: CP queue priority controls 



Translate queue priority into pipe priority and write to MQDs.
The priority values are used to perform queue and pipe arbitration.

Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bb2d2128

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c

+20 −0
Original line number Diff line number Diff line
@@ -25,6 +25,26 @@ 
#include "amdgpu_amdkfd.h"

#include "kfd_device_queue_manager.h"



/* Mapping queue priority to pipe priority, indexed by queue priority */

int pipe_priority_map[] = {

	KFD_PIPE_PRIORITY_CS_LOW,

	KFD_PIPE_PRIORITY_CS_LOW,

	KFD_PIPE_PRIORITY_CS_LOW,

	KFD_PIPE_PRIORITY_CS_LOW,

	KFD_PIPE_PRIORITY_CS_LOW,

	KFD_PIPE_PRIORITY_CS_LOW,

	KFD_PIPE_PRIORITY_CS_LOW,

	KFD_PIPE_PRIORITY_CS_MEDIUM,

	KFD_PIPE_PRIORITY_CS_MEDIUM,

	KFD_PIPE_PRIORITY_CS_MEDIUM,

	KFD_PIPE_PRIORITY_CS_MEDIUM,

	KFD_PIPE_PRIORITY_CS_HIGH,

	KFD_PIPE_PRIORITY_CS_HIGH,

	KFD_PIPE_PRIORITY_CS_HIGH,

	KFD_PIPE_PRIORITY_CS_HIGH,

	KFD_PIPE_PRIORITY_CS_HIGH

};



struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_dev *dev)

{

	struct kfd_mem_obj *mqd_mem_obj = NULL;

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ 
 * per KFD_MQD_TYPE for each device.

 *

 */



extern int pipe_priority_map[];

struct mqd_manager {

	int	(*init_mqd)(struct mqd_manager *mm, void **mqd,

			struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c

+9 −3
Original line number Diff line number Diff line
@@ -66,6 +66,12 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, 
		m->compute_static_thread_mgmt_se3);

}



static void set_priority(struct cik_mqd *m, struct queue_properties *q)

{

	m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];

	m->cp_hqd_queue_priority = q->priority;

}



static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,

					struct queue_properties *q)

{
@@ -81,7 +87,6 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 
	return mqd_mem_obj;

}





static int init_mqd(struct mqd_manager *mm, void **mqd,

		struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,

		struct queue_properties *q)
@@ -131,8 +136,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, 
	 * 1 = CS_MEDIUM (typically between HP3D and GFX

	 * 2 = CS_HIGH (typically above HP3D)

	 */

	m->cp_hqd_pipe_priority = 1;

	m->cp_hqd_queue_priority = 15;

	set_priority(m, q);



	if (q->format == KFD_QUEUE_FORMAT_AQL)

		m->cp_hqd_iq_rptr = AQL_ENABLE;
@@ -230,6 +234,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, 
		m->cp_hqd_pq_control |= NO_UPDATE_RPTR;



	update_cu_mask(mm, mqd, q);

	set_priority(m, q);



	q->is_active = QUEUE_IS_ACTIVE(*q);
@@ -354,6 +359,7 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, 


	q->is_active = QUEUE_IS_ACTIVE(*q);



	set_priority(m, q);

	return 0;

}

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c

+9 −3
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include "gca/gfx_8_0_sh_mask.h"

#include "gca/gfx_8_0_enum.h"

#include "oss/oss_3_0_sh_mask.h"



#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8



static inline struct vi_mqd *get_mqd(void *mqd)
@@ -68,6 +69,12 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, 
		m->compute_static_thread_mgmt_se3);

}



static void set_priority(struct vi_mqd *m, struct queue_properties *q)

{

	m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];

	m->cp_hqd_queue_priority = q->priority;

}



static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,

					struct queue_properties *q)

{
@@ -121,9 +128,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd, 
			1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |

			10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;



	m->cp_hqd_pipe_priority = 1;

	m->cp_hqd_queue_priority = 15;



	set_priority(m, q);

	m->cp_hqd_eop_rptr = 1 << CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT;



	if (q->format == KFD_QUEUE_FORMAT_AQL)
@@ -237,6 +242,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, 
			mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT;



	update_cu_mask(mm, mqd, q);

	set_priority(m, q);



	q->is_active = QUEUE_IS_ACTIVE(*q);

drivers/gpu/drm/amd/amdkfd/kfd_priv.h

+11 −0
Original line number Diff line number Diff line
@@ -348,6 +348,11 @@ enum kfd_queue_format { 
	KFD_QUEUE_FORMAT_AQL

};



enum KFD_QUEUE_PRIORITY {

	KFD_QUEUE_PRIORITY_MINIMUM = 0,

	KFD_QUEUE_PRIORITY_MAXIMUM = 15

};



/**

 * struct queue_properties

 *
@@ -499,6 +504,12 @@ enum KFD_MQD_TYPE { 
	KFD_MQD_TYPE_MAX

};



enum KFD_PIPE_PRIORITY {

	KFD_PIPE_PRIORITY_CS_LOW = 0,

	KFD_PIPE_PRIORITY_CS_MEDIUM,

	KFD_PIPE_PRIORITY_CS_HIGH

};



struct scheduling_resources {

	unsigned int vmid_mask;

	enum kfd_queue_type type;

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