Commit 0cab8d26 authored by Thinh Nguyen's avatar Thinh Nguyen Committed by Felipe Balbi
Browse files

usb: dwc3: Update DWC_usb31 GTXFIFOSIZ reg fields 



Update two GTXFIFOSIZ bit fields for the DWC_usb31 controller. TXFDEP
is a 15-bit value instead of 16-bit value, and bit 15 is TXFRAMNUM.

The GTXFIFOSIZ register for DWC_usb31 is as follows:
 +-------+-----------+----------------------------------+
 | BITS  | Name      | Description                      |
 +=======+===========+==================================+
 | 31:16 | TXFSTADDR | Transmit FIFOn RAM Start Address |
 | 15    | TXFRAMNUM | Asynchronous/Periodic TXFIFO     |
 | 14:0  | TXFDEP    | TXFIFO Depth                     |
 +-------+-----------+----------------------------------+

Signed-off-by: default avatarThinh Nguyen <thinhn@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent fab38333

drivers/usb/dwc3/core.h

+2 −0
Original line number Diff line number Diff line
@@ -255,6 +255,8 @@ 
#define DWC3_GUSB3PIPECTL_TX_DEEPH(n)	((n) << 1)



/* Global TX Fifo Size Register */

#define DWC31_GTXFIFOSIZ_TXFRAMNUM	BIT(15)		/* DWC_usb31 only */

#define DWC31_GTXFIFOSIZ_TXFDEF(n)	((n) & 0x7fff)	/* DWC_usb31 only */

#define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)

#define DWC3_GTXFIFOSIZ_TXFSTADDR(n)	((n) & 0xffff0000)

CRA Git | Maintained and supported by SUSTech CRA and CCSE