arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194 (0c988b73) · Commits · 戴 / test

arch/arm64/boot/dts/nvidia/tegra194.dtsi

+99 −0

Original line number	Diff line number	Diff line
		@@ -1620,6 +1620,105 @@
		0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
		};

		pcie_ep@14160000 {
		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
		reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
		0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
		0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */
		0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
		reg-names = "appl", "atu_dma", "dbi", "addr_space";

		status = "disabled";

		num-lanes = <4>;
		num-ib-windows = <2>;
		num-ob-windows = <8>;

		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
		clock-names = "core";

		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
		<&bpmp TEGRA194_RESET_PEX0_CORE_4>;
		reset-names = "apb", "core";

		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
		interrupt-names = "intr";

		nvidia,bpmp = <&bpmp 4>;

		nvidia,aspm-cmrt-us = <60>;
		nvidia,aspm-pwr-on-t-us = <20>;
		nvidia,aspm-l0s-entrance-latency-us = <3>;
		};

		pcie_ep@14180000 {
		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
		reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
		0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
		0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */
		0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
		reg-names = "appl", "atu_dma", "dbi", "addr_space";

		status = "disabled";

		num-lanes = <8>;
		num-ib-windows = <2>;
		num-ob-windows = <8>;

		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
		clock-names = "core";

		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
		<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
		reset-names = "apb", "core";

		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
		interrupt-names = "intr";

		nvidia,bpmp = <&bpmp 0>;

		nvidia,aspm-cmrt-us = <60>;
		nvidia,aspm-pwr-on-t-us = <20>;
		nvidia,aspm-l0s-entrance-latency-us = <3>;
		};

		pcie_ep@141a0000 {
		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
		reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
		0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
		0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
		0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
		reg-names = "appl", "atu_dma", "dbi", "addr_space";

		status = "disabled";

		num-lanes = <8>;
		num-ib-windows = <2>;
		num-ob-windows = <8>;

		pinctrl-names = "default";
		pinctrl-0 = <&clkreq_c5_bi_dir_state>;

		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
		clock-names = "core";

		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
		<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
		reset-names = "apb", "core";

		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
		interrupt-names = "intr";

		nvidia,bpmp = <&bpmp 5>;

		nvidia,aspm-cmrt-us = <60>;
		nvidia,aspm-pwr-on-t-us = <20>;
		nvidia,aspm-l0s-entrance-latency-us = <3>;
		};

		sysram@40000000 {
		compatible = "nvidia,tegra194-sysram", "mmio-sram";
		reg = <0x0 0x40000000 0x0 0x50000>;

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