Commit 0c91621c authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/gt: Pass intel_gt to pm routines 



Switch from passing the i915 container to newly named struct intel_gt.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190625130128.11009-2-chris@chris-wilson.co.uk
parent 8e9c2f62

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

+2 −2
Original line number Diff line number Diff line
@@ -2437,7 +2437,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, 
	 * wakeref that we hold until the GPU has been idle for at least

	 * 100ms.

	 */

	intel_gt_pm_get(eb.i915);

	intel_gt_pm_get(&eb.i915->gt);



	err = i915_mutex_lock_interruptible(dev);

	if (err)
@@ -2607,7 +2607,7 @@ err_engine: 
err_unlock:

	mutex_unlock(&dev->struct_mutex);

err_rpm:

	intel_gt_pm_put(eb.i915);

	intel_gt_pm_put(&eb.i915->gt);

	i915_gem_context_put(eb.gem_context);

err_destroy:

	eb_destroy(&eb);

drivers/gpu/drm/i915/gem/i915_gem_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -258,7 +258,7 @@ void i915_gem_resume(struct drm_i915_private *i915) 
	 * guarantee that the context image is complete. So let's just reset

	 * it and start again.

	 */

	intel_gt_resume(i915);

	intel_gt_resume(&i915->gt);



	if (i915_gem_init_hw(i915))

		goto err_wedged;

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c

+2 −2
Original line number Diff line number Diff line
@@ -379,7 +379,7 @@ static void disable_retire_worker(struct drm_i915_private *i915) 
{

	i915_gem_shrinker_unregister(i915);



	intel_gt_pm_get(i915);

	intel_gt_pm_get(&i915->gt);



	cancel_delayed_work_sync(&i915->gem.retire_work);

	flush_work(&i915->gem.idle_work);
@@ -387,7 +387,7 @@ static void disable_retire_worker(struct drm_i915_private *i915) 


static void restore_retire_worker(struct drm_i915_private *i915)

{

	intel_gt_pm_put(i915);

	intel_gt_pm_put(&i915->gt);



	mutex_lock(&i915->drm.struct_mutex);

	igt_flush_test(i915, I915_WAIT_LOCKED);

drivers/gpu/drm/i915/gt/intel_engine_pm.c

+4 −4
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ static int __engine_unpark(struct intel_wakeref *wf) 


	GEM_TRACE("%s\n", engine->name);



	intel_gt_pm_get(engine->i915);

	intel_gt_pm_get(engine->gt);



	/* Pin the default state for fast resets from atomic context. */

	map = NULL;
@@ -129,7 +129,7 @@ static int __engine_park(struct intel_wakeref *wf) 


	engine->execlists.no_priolist = false;



	intel_gt_pm_put(engine->i915);

	intel_gt_pm_put(engine->gt);

	return 0;

}
@@ -149,7 +149,7 @@ int intel_engines_resume(struct drm_i915_private *i915) 
	enum intel_engine_id id;

	int err = 0;



	intel_gt_pm_get(i915);

	intel_gt_pm_get(&i915->gt);

	for_each_engine(engine, i915, id) {

		intel_engine_pm_get(engine);

		engine->serial++; /* kernel context lost */
@@ -162,7 +162,7 @@ int intel_engines_resume(struct drm_i915_private *i915) 
			break;

		}

	}

	intel_gt_pm_put(i915);

	intel_gt_pm_put(&i915->gt);



	return err;

}

drivers/gpu/drm/i915/gt/intel_gt_pm.c

+14 −10
Original line number Diff line number Diff line
@@ -50,9 +50,11 @@ static int intel_gt_unpark(struct intel_wakeref *wf) 
	return 0;

}



void intel_gt_pm_get(struct drm_i915_private *i915)

void intel_gt_pm_get(struct intel_gt *gt)

{

	intel_wakeref_get(&i915->runtime_pm, &i915->gt.wakeref, intel_gt_unpark);

	struct intel_runtime_pm *rpm = &gt->i915->runtime_pm;



	intel_wakeref_get(rpm, &gt->wakeref, intel_gt_unpark);

}



static int intel_gt_park(struct intel_wakeref *wf)
@@ -75,9 +77,11 @@ static int intel_gt_park(struct intel_wakeref *wf) 
	return 0;

}



void intel_gt_pm_put(struct drm_i915_private *i915)

void intel_gt_pm_put(struct intel_gt *gt)

{

	intel_wakeref_put(&i915->runtime_pm, &i915->gt.wakeref, intel_gt_park);

	struct intel_runtime_pm *rpm = &gt->i915->runtime_pm;



	intel_wakeref_put(rpm, &gt->wakeref, intel_gt_park);

}



void intel_gt_pm_init_early(struct intel_gt *gt)
@@ -96,7 +100,7 @@ static bool reset_engines(struct drm_i915_private *i915) 


/**

 * intel_gt_sanitize: called after the GPU has lost power

 * @i915: the i915 device

 * @gt: the i915 GT container

 * @force: ignore a failed reset and sanitize engine state anyway

 *

 * Anytime we reset the GPU, either with an explicit GPU reset or through a
@@ -104,21 +108,21 @@ static bool reset_engines(struct drm_i915_private *i915) 
 * to match. Note that calling intel_gt_sanitize() if the GPU has not

 * been reset results in much confusion!

 */

void intel_gt_sanitize(struct drm_i915_private *i915, bool force)

void intel_gt_sanitize(struct intel_gt *gt, bool force)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;



	GEM_TRACE("\n");



	if (!reset_engines(i915) && !force)

	if (!reset_engines(gt->i915) && !force)

		return;



	for_each_engine(engine, i915, id)

	for_each_engine(engine, gt->i915, id)

		intel_engine_reset(engine, false);

}



void intel_gt_resume(struct drm_i915_private *i915)

void intel_gt_resume(struct intel_gt *gt)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;
@@ -129,7 +133,7 @@ void intel_gt_resume(struct drm_i915_private *i915) 
	 * Only the kernel contexts should remain pinned over suspend,

	 * allowing us to fixup the user contexts on their first pin.

	 */

	for_each_engine(engine, i915, id) {

	for_each_engine(engine, gt->i915, id) {

		struct intel_context *ce;



		ce = engine->kernel_context;

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