drm/amd/display: Program v_total_min/max after v_total_cntl (0c8df4bb) · Commits · 戴 / test

drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c

+8 −8

Original line number	Diff line number	Diff line
		@@ -431,14 +431,6 @@ void dce110_timing_generator_set_drr(
		0,
		CRTC_V_TOTAL_CONTROL,
		CRTC_SET_V_TOTAL_MIN_MASK);
		set_reg_field_value(v_total_min,
		0,
		CRTC_V_TOTAL_MIN,
		CRTC_V_TOTAL_MIN);
		set_reg_field_value(v_total_max,
		0,
		CRTC_V_TOTAL_MAX,
		CRTC_V_TOTAL_MAX);
		set_reg_field_value(v_total_cntl,
		0,
		CRTC_V_TOTAL_CONTROL,
		@@ -447,6 +439,14 @@ void dce110_timing_generator_set_drr(
		0,
		CRTC_V_TOTAL_CONTROL,
		CRTC_V_TOTAL_MAX_SEL);
		set_reg_field_value(v_total_min,
		0,
		CRTC_V_TOTAL_MIN,
		CRTC_V_TOTAL_MIN);
		set_reg_field_value(v_total_max,
		0,
		CRTC_V_TOTAL_MAX,
		CRTC_V_TOTAL_MAX);
		set_reg_field_value(v_total_cntl,
		0,
		CRTC_V_TOTAL_CONTROL,

+6 −6

Original line number	Diff line number	Diff line
		@@ -570,18 +570,18 @@ void dce120_timing_generator_set_drr(
		0x180);

		} else {
		CRTC_REG_UPDATE(
		CRTC0_CRTC_V_TOTAL_MIN,
		CRTC_V_TOTAL_MIN, 0);
		CRTC_REG_UPDATE(
		CRTC0_CRTC_V_TOTAL_MAX,
		CRTC_V_TOTAL_MAX, 0);
		CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 5,
		FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0,
		FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0,
		FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
		FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
		FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
		CRTC_REG_UPDATE(
		CRTC0_CRTC_V_TOTAL_MIN,
		CRTC_V_TOTAL_MIN, 0);
		CRTC_REG_UPDATE(
		CRTC0_CRTC_V_TOTAL_MAX,
		CRTC_V_TOTAL_MAX, 0);
		CRTC_REG_UPDATE(
		CRTC0_CRTC_STATIC_SCREEN_CONTROL,
		CRTC_STATIC_SCREEN_EVENT_MASK,

+6 −6

Original line number	Diff line number	Diff line
		@@ -855,17 +855,17 @@ void optc1_set_drr(
		OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
		OTG_SET_V_TOTAL_MIN_MASK, 0);
		} else {
		REG_SET(OTG_V_TOTAL_MIN, 0,
		OTG_V_TOTAL_MIN, 0);

		REG_SET(OTG_V_TOTAL_MAX, 0,
		OTG_V_TOTAL_MAX, 0);

		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
		OTG_SET_V_TOTAL_MIN_MASK, 0,
		OTG_V_TOTAL_MIN_SEL, 0,
		OTG_V_TOTAL_MAX_SEL, 0,
		OTG_FORCE_LOCK_ON_EVENT, 0);

		REG_SET(OTG_V_TOTAL_MIN, 0,
		OTG_V_TOTAL_MIN, 0);

		REG_SET(OTG_V_TOTAL_MAX, 0,
		OTG_V_TOTAL_MAX, 0);
		}
		}