dt-binding: clock: Document canaan,k210-clk bindings

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/canaan,k210-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Canaan Kendryte K210 Clock Device Tree Bindings

maintainers:

  - Damien Le Moal <damien.lemoal@wdc.com>

description: |

  Canaan Kendryte K210 SoC clocks driver bindings. The clock

  controller node must be defined as a child node of the K210

  system controller node.

  See also:

  - dt-bindings/clock/k210-clk.h

properties:

  compatible:

    const: canaan,k210-clk

  clocks:

    description:

      Phandle of the SoC 26MHz fixed-rate oscillator clock.

  '#clock-cells':

    const: 1

required:

  - compatible

  - '#clock-cells'

  - clocks

additionalProperties: false

examples:

  - |

    #include <dt-bindings/clock/k210-clk.h>

    clocks {

      in0: oscillator {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <26000000>;

      };

    };

    /* ... */

    sysclk: clock-controller {

      #clock-cells = <1>;

      compatible = "canaan,k210-clk";

      clocks = <&in0>;

    };

 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>

 * Copyright (c) 2020 Western Digital Corporation or its affiliates.

 */

#ifndef K210_CLK_H

#define K210_CLK_H

#ifndef CLOCK_K210_CLK_H

#define CLOCK_K210_CLK_H

/*

 * Arbitrary identifiers for clocks.

 * The structure is: in0 -> pll0 -> aclk -> cpu

 *

 * Since we use the hardware defaults for now, set all these to the same clock.

 * Kendryte K210 SoC clock identifiers (arbitrary values).

 */

#define K210_CLK_PLL0   0

#define K210_CLK_PLL1   0

#define K210_CLK_ACLK	0

#define K210_CLK_CPU	0

#define K210_CLK_SRAM0	1

#define K210_CLK_SRAM1	2

#define K210_CLK_AI	3

#define K210_CLK_DMA	4

#define K210_CLK_FFT	5

#define K210_CLK_ROM	6

#define K210_CLK_DVP	7

#define K210_CLK_APB0	8

#define K210_CLK_APB1	9

#define K210_CLK_APB2	10

#define K210_CLK_I2S0	11

#define K210_CLK_I2S1	12

#define K210_CLK_I2S2	13

#define K210_CLK_I2S0_M	14

#define K210_CLK_I2S1_M	15

#define K210_CLK_I2S2_M	16

#define K210_CLK_WDT0	17

#define K210_CLK_WDT1	18

#define K210_CLK_SPI0	19

#define K210_CLK_SPI1	20

#define K210_CLK_SPI2	21

#define K210_CLK_I2C0	22

#define K210_CLK_I2C1	23

#define K210_CLK_I2C2	24

#define K210_CLK_SPI3	25

#define K210_CLK_TIMER0	26

#define K210_CLK_TIMER1	27

#define K210_CLK_TIMER2	28

#define K210_CLK_GPIO	29

#define K210_CLK_UART1	30

#define K210_CLK_UART2	31

#define K210_CLK_UART3	32

#define K210_CLK_FPIOA	33

#define K210_CLK_SHA	34

#define K210_CLK_AES	35

#define K210_CLK_OTP	36

#define K210_CLK_RTC	37

#endif /* K210_CLK_H */

#define K210_NUM_CLKS	38

#endif /* CLOCK_K210_CLK_H */