Commit 0c6c8878 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://github.com/openrisc/linux 

Pull OpenRISC updates from Stafford Horne:

 - New drivers and OpenRISC support for the LiteX platform

 - A bug fix to support userspace gdb debugging

 - Fixes one compile issue with blk-iocost

* tag 'for-linus' of git://github.com/openrisc/linux:
  openrisc: add local64.h to fix blk-iocost build
  openrisc: fix trap for debugger breakpoint signalling
  openrisc: add support for LiteX
  drivers/tty/serial: add LiteUART driver
  dt-bindings: serial: document LiteUART bindings
  drivers/soc/litex: add LiteX SoC Controller driver
  dt-bindings: soc: document LiteX SoC Controller bindings
  dt-bindings: vendor: add vendor prefix for LiteX
parents 8a5be36b d8398bf8

Documentation/devicetree/bindings/serial/litex,liteuart.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause



%YAML 1.2

---

$id: http://devicetree.org/schemas/serial/litex,liteuart.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: LiteUART serial controller



maintainers:

  - Karol Gugala <kgugala@antmicro.com>

  - Mateusz Holenko <mholenko@antmicro.com>



description: |

  LiteUART serial controller is a part of the LiteX FPGA SoC builder. It supports

  multiple CPU architectures, currently including e.g. OpenRISC and RISC-V.



properties:

  compatible:

    const: litex,liteuart



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg



examples:

  - |

    uart0: serial@e0001800 {

      compatible = "litex,liteuart";

      reg = <0xe0001800 0x100>;

      interrupts = <2>;

    };

Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

# Copyright 2020 Antmicro <www.antmicro.com>

%YAML 1.2

---

$id: "http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: LiteX SoC Controller driver



description: |

  This is the SoC Controller driver for the LiteX SoC Builder.

  Its purpose is to verify LiteX CSR (Control&Status Register) access

  operations and provide functions for other drivers to read/write CSRs

  and to check if those accessors are ready to be used.



maintainers:

  - Karol Gugala <kgugala@antmicro.com>

  - Mateusz Holenko <mholenko@antmicro.com>



properties:

  compatible:

    const: litex,soc-controller



  reg:

    maxItems: 1



required:

  - compatible

  - reg



examples:

  - |

    soc_ctrl0: soc-controller@f0000000 {

        compatible = "litex,soc-controller";

        reg = <0xf0000000 0xc>;

        status = "okay";

    };



...

Documentation/devicetree/bindings/vendor-prefixes.yaml

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@@ -621,6 +621,8 @@ patternProperties: 
    description: Linux-specific binding

  "^linx,.*":

    description: Linx Technologies

  "^litex,.*":

    description: LiteX SoC builder

  "^lltc,.*":

    description: Linear Technology Corporation

  "^logicpd,.*":

MAINTAINERS

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@@ -10264,6 +10264,16 @@ L: kunit-dev@googlegroups.com 
S:	Maintained

F:	lib/list-test.c









LITEX PLATFORM









M:	Karol Gugala <kgugala@antmicro.com>









M:	Mateusz Holenko <mholenko@antmicro.com>









S:	Maintained









F:	Documentation/devicetree/bindings/*/litex,*.yaml









F:	arch/openrisc/boot/dts/or1klitex.dts









F:	drivers/soc/litex/litex_soc_ctrl.c









F:	drivers/tty/serial/liteuart.c









F:	include/linux/litex.h

















LIVE PATCHING









M:	Josh Poimboeuf <jpoimboe@redhat.com>









M:	Jiri Kosina <jikos@kernel.org>
































arch/openrisc/boot/dts/or1klitex.dts
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+55
−0






























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// SPDX-License-Identifier: GPL-2.0









/*









 * LiteX-based System on Chip









 *









 * Copyright (C) 2019 Antmicro <www.antmicro.com>









 */



















/dts-v1/;









/ {









	compatible = "opencores,or1ksim";









	#address-cells = <1>;









	#size-cells = <1>;









	interrupt-parent = <&pic>;



















	aliases {









		serial0 = &serial0;









	};



















	chosen {









		bootargs = "console=liteuart";









	};



















	memory@0 {









		device_type = "memory";









		reg = <0x00000000 0x10000000>;









	};



















	cpus {









		#address-cells = <1>;









		#size-cells = <0>;









		cpu@0 {









			compatible = "opencores,or1200-rtlsvn481";









			reg = <0>;









			clock-frequency = <100000000>;









		};









	};



















	pic: pic {









		compatible = "opencores,or1k-pic";









		#interrupt-cells = <1>;









		interrupt-controller;









	};



















	serial0: serial@e0002000 {









		device_type = "serial";









		compatible = "litex,liteuart";









		reg = <0xe0002000 0x100>;









	};



















	soc_ctrl0: soc_controller@e0000000 {









			compatible = "litex,soc-controller";









			reg = <0xe0000000 0xc>;









			status = "okay";









	};









};
































































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