Commit 0c0dab86 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn2.5: implement indirect DPG SRAM mode 



Implement indirect DPG SRAM mode for vcn2.5

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8484df96

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+3 −0
Original line number Diff line number Diff line
@@ -75,6 +75,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 
		break;

	case CHIP_ARCTURUS:

		fw_name = FIRMWARE_ARCTURUS;

		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&

		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))

			adev->vcn.indirect_sram = true;

		break;

	case CHIP_RENOIR:

		fw_name = FIRMWARE_RENOIR;

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

+49 −20
Original line number Diff line number Diff line
@@ -433,6 +433,7 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx 


	/* cache window 0: fw */

	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {

		if (!indirect) {

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

				UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),

				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
@@ -441,6 +442,14 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx 
				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

				UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);

		} else {

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

				UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

				UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);

			WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

				UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);

		}

		offset = 0;

	} else {

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
@@ -455,10 +464,15 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx 
			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);

	}



	if (!indirect)

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);

	else

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);



	/* cache window 1: stack */

	if (!indirect) {

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),

			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
@@ -467,7 +481,14 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx 
			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);



	} else {

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);

		WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

			UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);

	}

	WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(

		UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
@@ -740,6 +761,9 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo 
	tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;

	WREG32_SOC15(UVD, inst_idx, mmUVD_POWER_STATUS, tmp);



	if (indirect)

		adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;



	/* enable clock gating */

	vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
@@ -815,6 +839,11 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo 
		UVD, inst_idx, mmUVD_MASTINT_EN),

		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);



	if (indirect)

		psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,

				    (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -

					       (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));



	ring = &adev->vcn.inst[inst_idx].ring_dec;

	/* force RBC into idle state */

	rb_bufsz = order_base_2(ring->ring_size);
@@ -863,7 +892,7 @@ static int vcn_v2_5_start(struct amdgpu_device *adev) 
		if (adev->vcn.harvest_config & (1 << i))

			continue;

		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)

			return vcn_v2_5_start_dpg_mode(adev, i, 0);

			return vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);



		/* disable register anti-hang mechanism */

		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,

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