Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/spi-2.6

PXA2xx SPI on SSP driver HOWTO

===================================================

This a mini howto on the pxa2xx_spi driver.  The driver turns a PXA2xx

synchronous serial port into a SPI master controller

(see Documentation/spi/spi_summary). The driver has the following features

- Support for any PXA2xx SSP

- SSP PIO and SSP DMA data transfers.

- External and Internal (SSPFRM) chip selects.

- Per slave device (chip) configuration.

- Full suspend, freeze, resume support.

The driver is built around a "spi_message" fifo serviced by workqueue and a

tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet

(pump_transfer) is responsible for queuing SPI transactions and setting up and

launching the dma/interrupt driven transfers.

Declaring PXA2xx Master Controllers

-----------------------------------

Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a

"platform device".  The master configuration is passed to the driver via a table

found in include/asm-arm/arch-pxa/pxa2xx_spi.h:

struct pxa2xx_spi_master {

	enum pxa_ssp_type ssp_type;

	u32 clock_enable;

	u16 num_chipselect;

	u8 enable_dma;

};

The "pxa2xx_spi_master.ssp_type" field must have a value between 1 and 3 and

informs the driver which features a particular SSP supports.

The "pxa2xx_spi_master.clock_enable" field is used to enable/disable the

corresponding SSP peripheral block in the "Clock Enable Register (CKEN"). See

the "PXA2xx Developer Manual" section "Clocks and Power Management".

The "pxa2xx_spi_master.num_chipselect" field is used to determine the number of

slave device (chips) attached to this SPI master.

The "pxa2xx_spi_master.enable_dma" field informs the driver that SSP DMA should

be used.  This caused the driver to acquire two DMA channels: rx_channel and

tx_channel.  The rx_channel has a higher DMA service priority the tx_channel.

See the "PXA2xx Developer Manual" section "DMA Controller".

NSSP MASTER SAMPLE

------------------

Below is a sample configuration using the PXA255 NSSP.

static struct resource pxa_spi_nssp_resources[] = {

	[0] = {

		.start	= __PREG(SSCR0_P(2)), /* Start address of NSSP */

		.end	= __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */

		.flags	= IORESOURCE_MEM,

	},

	[1] = {

		.start	= IRQ_NSSP, /* NSSP IRQ */

		.end	= IRQ_NSSP,

		.flags	= IORESOURCE_IRQ,

	},

};

static struct pxa2xx_spi_master pxa_nssp_master_info = {

	.ssp_type = PXA25x_NSSP, /* Type of SSP */

	.clock_enable = CKEN9_NSSP, /* NSSP Peripheral clock */

	.num_chipselect = 1, /* Matches the number of chips attached to NSSP */

	.enable_dma = 1, /* Enables NSSP DMA */

};

static struct platform_device pxa_spi_nssp = {

	.name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */

	.id = 2, /* Bus number, MUST MATCH SSP number 1..n */

	.resource = pxa_spi_nssp_resources,

	.num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),

	.dev = {

		.platform_data = &pxa_nssp_master_info, /* Passed to driver */

	},

};

static struct platform_device *devices[] __initdata = {

	&pxa_spi_nssp,

};

static void __init board_init(void)

{

	(void)platform_add_device(devices, ARRAY_SIZE(devices));

}

Declaring Slave Devices

-----------------------

Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c

using the "spi_board_info" structure found in "linux/spi/spi.h". See

"Documentation/spi/spi_summary" for additional information.

Each slave device attached to the PXA must provide slave specific configuration

information via the structure "pxa2xx_spi_chip" found in

"include/asm-arm/arch-pxa/pxa2xx_spi.h".  The pxa2xx_spi master controller driver

will uses the configuration whenever the driver communicates with the slave

device.

struct pxa2xx_spi_chip {

	u8 tx_threshold;

	u8 rx_threshold;

	u8 dma_burst_size;

	u32 timeout_microsecs;

	u8 enable_loopback;

	void (*cs_control)(u32 command);

};

The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are

used to configure the SSP hardware fifo.  These fields are critical to the

performance of pxa2xx_spi driver and misconfiguration will result in rx

fifo overruns (especially in PIO mode transfers). Good default values are

	.tx_threshold = 12,

	.rx_threshold = 4,

The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA

engine and is related the "spi_device.bits_per_word" field.  Read and understand

the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers

to determine the correct value. An SSP configured for byte-wide transfers would

use a value of 8.

The "pxa2xx_spi_chip.timeout_microsecs" fields is used to efficiently handle

trailing bytes in the SSP receiver fifo.  The correct value for this field is

dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific

slave device.  Please note the the PXA2xx SSP 1 does not support trailing byte

timeouts and must busy-wait any trailing bytes.

The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting

into internal loopback mode.  In this mode the SSP controller internally

connects the SSPTX pin the the SSPRX pin.  This is useful for initial setup

testing.

The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific

function for asserting/deasserting a slave device chip select.  If the field is

NULL, the pxa2xx_spi master controller driver assumes that the SSP port is

configured to use SSPFRM instead.

NSSP SALVE SAMPLE

-----------------

The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the

"spi_board_info.controller_data" field. Below is a sample configuration using

the PXA255 NSSP.

/* Chip Select control for the CS8415A SPI slave device */

static void cs8415a_cs_control(u32 command)

{

	if (command & PXA2XX_CS_ASSERT)

		GPCR(2) = GPIO_bit(2);

	else

		GPSR(2) = GPIO_bit(2);

}

/* Chip Select control for the CS8405A SPI slave device */

static void cs8405a_cs_control(u32 command)

{

	if (command & PXA2XX_CS_ASSERT)

		GPCR(3) = GPIO_bit(3);

	else

		GPSR(3) = GPIO_bit(3);

}

static struct pxa2xx_spi_chip cs8415a_chip_info = {

	.tx_threshold = 12, /* SSP hardward FIFO threshold */

	.rx_threshold = 4, /* SSP hardward FIFO threshold */

	.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */

	.timeout_microsecs = 64, /* Wait at least 64usec to handle trailing */

	.cs_control = cs8415a_cs_control, /* Use external chip select */

};

static struct pxa2xx_spi_chip cs8405a_chip_info = {

	.tx_threshold = 12, /* SSP hardward FIFO threshold */

	.rx_threshold = 4, /* SSP hardward FIFO threshold */

	.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */

	.timeout_microsecs = 64, /* Wait at least 64usec to handle trailing */

	.cs_control = cs8405a_cs_control, /* Use external chip select */

};

static struct spi_board_info streetracer_spi_board_info[] __initdata = {

	{

		.modalias = "cs8415a", /* Name of spi_driver for this device */

		.max_speed_hz = 3686400, /* Run SSP as fast a possbile */

		.bus_num = 2, /* Framework bus number */

		.chip_select = 0, /* Framework chip select */

		.platform_data = NULL; /* No spi_driver specific config */

		.controller_data = &cs8415a_chip_info, /* Master chip config */

		.irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */

	},

	{

		.modalias = "cs8405a", /* Name of spi_driver for this device */

		.max_speed_hz = 3686400, /* Run SSP as fast a possbile */

		.bus_num = 2, /* Framework bus number */

		.chip_select = 1, /* Framework chip select */

		.controller_data = &cs8405a_chip_info, /* Master chip config */

		.irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */

	},

};

static void __init streetracer_init(void)

{

	spi_register_board_info(streetracer_spi_board_info,

				ARRAY_SIZE(streetracer_spi_board_info));

}

DMA and PIO I/O Support

-----------------------

The pxa2xx_spi driver support both DMA and interrupt driven PIO message

transfers.  The driver defaults to PIO mode and DMA transfers must enabled by

setting the "enable_dma" flag in the "pxa2xx_spi_master" structure and and

ensuring that the "pxa2xx_spi_chip.dma_burst_size" field is non-zero.  The DMA

mode support both coherent and stream based DMA mappings.

The following logic is used to determine the type of I/O to be used on

a per "spi_transfer" basis:

if !enable_dma or dma_burst_size == 0 then

	always use PIO transfers

if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then

	use coherent DMA mode

if rx_buf and tx_buf are aligned on 8 byte boundary then

	use streaming DMA mode

otherwise

	use PIO transfer

THANKS TO

---------

David Brownell and others for mentoring the development of this driver.

The driver will initialize the fields of that spi_master, including the

bus number (maybe the same as the platform device ID) and three methods

used to interact with the SPI core and SPI protocol drivers.  It will

also initialize its own internal state.

also initialize its own internal state.  (See below about bus numbering

and those methods.)

After you initialize the spi_master, then use spi_register_master() to

publish it to the rest of the system.  At that time, device nodes for

the controller and any predeclared spi devices will be made available,

and the driver model core will take care of binding them to drivers.

If you need to remove your SPI controller driver, spi_unregister_master()

will reverse the effect of spi_register_master().

BUS NUMBERING

Bus numbering is important, since that's how Linux identifies a given

SPI bus (shared SCK, MOSI, MISO).  Valid bus numbers start at zero.  On

SOC systems, the bus numbers should match the numbers defined by the chip

manufacturer.  For example, hardware controller SPI2 would be bus number 2,

and spi_board_info for devices connected to it would use that number.

If you don't have such hardware-assigned bus number, and for some reason

you can't just assign them, then provide a negative bus number.  That will

then be replaced by a dynamically assigned number. You'd then need to treat

this as a non-static configuration (see above).

SPI MASTER METHODS

    master->setup(struct spi_device *spi)

	This sets up the device clock rate, SPI mode, and word sizes.

	state it dynamically associates with that device.  If you do that,

	be sure to provide the cleanup() method to free that state.

SPI MESSAGE QUEUE

The bulk of the driver will be managing the I/O queue fed by transfer().

That queue could be purely conceptual.  For example, a driver used only

often DMA (especially if the root filesystem is in SPI flash), and

execution contexts like IRQ handlers, tasklets, or workqueues (such

as keventd).  Your driver can be as fancy, or as simple, as you need.

Such a transfer() method would normally just add the message to a

queue, and then start some asynchronous transfer engine (unless it's

already running).

THANKS TO

L:	alsa-devel@alsa-project.org

S:	Maintained

SPI SUBSYSTEM

P:	David Brownell

M:	dbrownell@users.sourceforge.net

L:	spi-devel-general@lists.sourceforge.net

S:	Maintained

TPM DEVICE DRIVER

P:	Kylene Hall

M:	kjhall@us.ibm.com

	  inexpensive battery powered microcontroller evaluation board.

	  This same cable can be used to flash new firmware.

config SPI_PXA2XX

	tristate "PXA2xx SSP SPI master"

	depends on SPI_MASTER && ARCH_PXA && EXPERIMENTAL

	help

	  This enables using a PXA2xx SSP port as a SPI master controller.

	  The driver can be configured to use any SSP port and additional

	  documentation can be found a Documentation/spi/pxa2xx.

#

# Add new SPI master controllers in alphabetical order above this line

#

# SPI master controller drivers (bus)

obj-$(CONFIG_SPI_BITBANG)		+= spi_bitbang.o

obj-$(CONFIG_SPI_BUTTERFLY)		+= spi_butterfly.o

obj-$(CONFIG_SPI_PXA2XX)		+= pxa2xx_spi.o

# 	... add above this line ...

# SPI protocol drivers (device/link on bus)