Commit 0bbb8176 authored Nov 24, 2015 by Eric Huang Committed by Alex Deucher Dec 21, 2015

drm/amd/amdgpu: enable uvd&vce clock gating for Fiji.



Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>

parent 0689a570

drivers/gpu/drm/amd/amdgpu/vi.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -1442,7 +1442,8 @@ static int vi_common_early_init(void *handle)
		break;
		case CHIP_FIJI:
		adev->has_uvd = true;
		adev->cg_flags = 0;
		adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG \|
		AMDGPU_CG_SUPPORT_VCE_MGCG;
		adev->pg_flags = 0;
		adev->external_rev_id = adev->rev_id + 0x3c;
		break;

Admin message