ARM: mv78xx0: use fixed pci i/o mapping (0b9b18e0) · Commits · 戴 / test

arch/arm/Kconfig

+0 −1

Original line number	Diff line number	Diff line
		@@ -571,7 +571,6 @@ config ARCH_MV78XX0
		select PCI
		select ARCH_REQUIRE_GPIOLIB
		select GENERIC_CLOCKEVENTS
		select NEED_MACH_IO_H
		select PLAT_ORION
		help
		Support for the following Marvell MV78xx0 series SoCs:

+2 −1

Original line number	Diff line number	Diff line
		@@ -13,6 +13,7 @@
		#include <linux/mbus.h>
		#include <linux/io.h>
		#include <plat/addr-map.h>
		#include <mach/mv78xx0.h>
		#include "common.h"

		/*
		@@ -81,7 +82,7 @@ void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
		int maj, int min)
		{
		orion_setup_cpu_win(&addr_map_cfg, window, base, size,
		TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
		TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
		}

		void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,

+0 −5

Original line number	Diff line number	Diff line
		@@ -134,11 +134,6 @@ static struct map_desc mv78xx0_io_desc[] __initdata = {
		.pfn = 0,
		.length = MV78XX0_CORE_REGS_SIZE,
		.type = MT_DEVICE,
		}, {
		.virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
		.pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
		.length = MV78XX0_PCIE_IO_SIZE * 8,
		.type = MT_DEVICE,
		}, {
		.virtual = MV78XX0_REGS_VIRT_BASE,
		.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),

deleted100644 → 0

+0 −24

Original line number	Diff line number	Diff line
		/*
		* arch/arm/mach-mv78xx0/include/mach/io.h
		*
		* This file is licensed under the terms of the GNU General Public
		* License version 2. This program is licensed "as is" without any
		* warranty of any kind, whether express or implied.
		*/

		#ifndef __ASM_ARCH_IO_H
		#define __ASM_ARCH_IO_H

		#include "mv78xx0.h"

		#define IO_SPACE_LIMIT 0xffffffff

		static inline void __iomem *__io(unsigned long addr)
		{
		return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
		+ MV78XX0_PCIE_IO_VIRT_BASE(0));
		}

		#define __io(a) __io(a)

		#endif

+10 −11

Original line number	Diff line number	Diff line
		@@ -29,15 +29,15 @@
		*
		* virt phys size
		* fe400000 f102x000 16K core-specific peripheral registers
		* fe700000 f0800000 1M PCIe #0 I/O space
		* fe800000 f0900000 1M PCIe #1 I/O space
		* fe900000 f0a00000 1M PCIe #2 I/O space
		* fea00000 f0b00000 1M PCIe #3 I/O space
		* feb00000 f0c00000 1M PCIe #4 I/O space
		* fec00000 f0d00000 1M PCIe #5 I/O space
		* fed00000 f0e00000 1M PCIe #6 I/O space
		* fee00000 f0f00000 1M PCIe #7 I/O space
		* fef00000 f1000000 1M on-chip peripheral registers
		* fee00000 f0800000 64K PCIe #0 I/O space
		* fee10000 f0900000 64K PCIe #1 I/O space
		* fee20000 f0a00000 64K PCIe #2 I/O space
		* fee30000 f0b00000 64K PCIe #3 I/O space
		* fee40000 f0c00000 64K PCIe #4 I/O space
		* fee50000 f0d00000 64K PCIe #5 I/O space
		* fee60000 f0e00000 64K PCIe #6 I/O space
		* fee70000 f0f00000 64K PCIe #7 I/O space
		* fd000000 f1000000 1M on-chip peripheral registers
		*/
		#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
		#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
		@@ -46,11 +46,10 @@
		#define MV78XX0_CORE_REGS_SIZE SZ_16K

		#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
		#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20))
		#define MV78XX0_PCIE_IO_SIZE SZ_1M

		#define MV78XX0_REGS_PHYS_BASE 0xf1000000
		#define MV78XX0_REGS_VIRT_BASE 0xfef00000
		#define MV78XX0_REGS_VIRT_BASE 0xfd000000
		#define MV78XX0_REGS_SIZE SZ_1M

		#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000