Unverified Commit 0b8e7bbd authored Nov 13, 2019 by Yunhao Tian Committed by Maxime Ripard Nov 13, 2019

drm/sun4i: tcon: Set min division of TCON0_DCLK to 1.



The datasheet of V3s (and various other chips) wrote
that TCON0_DCLK_DIV can be >= 1 if only dclk is used,
and must >= 6 if dclk1 or dclk2 is used. As currently
neither dclk1 nor dclk2 is used (no writes to these
bits), let's set minimal division to 1.

If this minimal division is 6, some common dot clock
frequencies can't be produced (e.g. 30MHz will not be
possible and will fallback to 25MHz), which is
obviously not an expected behaviour.

Signed-off-by: Yunhao Tian <t123yh@outlook.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/linux-arm-kernel/MN2PR08MB57905AD8A00C08DA219377C989760@MN2PR08MB5790.namprd08.prod.outlook.com/

parent 105401b6

drivers/gpu/drm/sun4i/sun4i_tcon.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -488,7 +488,7 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,

		WARN_ON(!tcon->quirks->has_channel_0);

		tcon->dclk_min_div = 6;
		tcon->dclk_min_div = 1;
		tcon->dclk_max_div = 127;
		sun4i_tcon0_mode_set_common(tcon, mode);

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