Unverified Commit 0b87d6bc authored by Vijendar Mukunda's avatar Vijendar Mukunda Committed by Mark Brown
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ASoC: amd: add acp3x pcm driver dma ops 



ACP3x has a DMA controller to access system memory.
This controller transfers data from/to system memory
to/from the ACP internal FIFO.
The patch adds PCM driver DMA operations.

Signed-off-by: default avatarMaruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Tested-by: default avatarRavulapati Vishnu vardhan Rao <Vishnuvardhanrao.Ravulapati@amd.com>
Signed-off-by: default avatarVijendar Mukunda <vijendar.mukunda@amd.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 32feac95

sound/soc/amd/raven/acp3x-pcm-dma.c

+255 −7
Original line number Diff line number Diff line
@@ -33,6 +33,54 @@ struct i2s_dev_data { 
	struct snd_pcm_substream *capture_stream;

};



struct i2s_stream_instance {

	u16 num_pages;

	u16 channels;

	u32 xfer_resolution;

	struct page *pg;

	void __iomem *acp3x_base;

};



static const struct snd_pcm_hardware acp3x_pcm_hardware_playback = {

	.info = SNDRV_PCM_INFO_INTERLEAVED |

		SNDRV_PCM_INFO_BLOCK_TRANSFER |

		SNDRV_PCM_INFO_BATCH |

		SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,

	.formats = SNDRV_PCM_FMTBIT_S16_LE |  SNDRV_PCM_FMTBIT_S8 |

		   SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |

		   SNDRV_PCM_FMTBIT_S32_LE,

	.channels_min = 2,

	.channels_max = 8,

	.rates = SNDRV_PCM_RATE_8000_96000,

	.rate_min = 8000,

	.rate_max = 96000,

	.buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,

	.period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,

	.period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,

	.periods_min = PLAYBACK_MIN_NUM_PERIODS,

	.periods_max = PLAYBACK_MAX_NUM_PERIODS,

};



static const struct snd_pcm_hardware acp3x_pcm_hardware_capture = {

	.info = SNDRV_PCM_INFO_INTERLEAVED |

		SNDRV_PCM_INFO_BLOCK_TRANSFER |

		SNDRV_PCM_INFO_BATCH |

	    SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,

	.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 |

		   SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE |

		   SNDRV_PCM_FMTBIT_S32_LE,

	.channels_min = 2,

	.channels_max = 2,

	.rates = SNDRV_PCM_RATE_8000_48000,

	.rate_min = 8000,

	.rate_max = 48000,

	.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,

	.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,

	.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,

	.periods_min = CAPTURE_MIN_NUM_PERIODS,

	.periods_max = CAPTURE_MAX_NUM_PERIODS,

};



static int acp3x_power_on(void __iomem *acp3x_base, bool on)

{

	u16 val, mask;
@@ -165,14 +213,214 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id) 
		return IRQ_NONE;

}



static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction)

{

	u16 page_idx;

	u64 addr;

	u32 low, high, val, acp_fifo_addr;

	struct page *pg = rtd->pg;



	/* 8 scratch registers used to map one 64 bit address */

	if (direction == SNDRV_PCM_STREAM_PLAYBACK)

		val = 0;

	else

		val = rtd->num_pages * 8;



	/* Group Enable */

	rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base +

		  mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1);

	rv_writel(PAGE_SIZE_4K_ENABLE, rtd->acp3x_base +

		  mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);



	for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {

		/* Load the low address of page int ACP SRAM through SRBM */

		addr = page_to_phys(pg);

		low = lower_32_bits(addr);

		high = upper_32_bits(addr);



		rv_writel(low, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val);

		high |= BIT(31);

		rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val

				+ 4);

		/* Move to next physically contiguos page */

		val += 8;

		pg++;

	}



	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {

		/* Config ringbuffer */

		rv_writel(MEM_WINDOW_START, rtd->acp3x_base +

			  mmACP_BT_TX_RINGBUFADDR);

		rv_writel(MAX_BUFFER, rtd->acp3x_base +

			  mmACP_BT_TX_RINGBUFSIZE);

		rv_writel(DMA_SIZE, rtd->acp3x_base + mmACP_BT_TX_DMA_SIZE);



		/* Config audio fifo */

		acp_fifo_addr = ACP_SRAM_PTE_OFFSET + (rtd->num_pages * 8)

				+ PLAYBACK_FIFO_ADDR_OFFSET;

		rv_writel(acp_fifo_addr, rtd->acp3x_base +

			  mmACP_BT_TX_FIFOADDR);

		rv_writel(FIFO_SIZE, rtd->acp3x_base + mmACP_BT_TX_FIFOSIZE);

	} else {

		/* Config ringbuffer */

		rv_writel(MEM_WINDOW_START + MAX_BUFFER, rtd->acp3x_base +

			  mmACP_BT_RX_RINGBUFADDR);

		rv_writel(MAX_BUFFER, rtd->acp3x_base +

			  mmACP_BT_RX_RINGBUFSIZE);

		rv_writel(DMA_SIZE, rtd->acp3x_base + mmACP_BT_RX_DMA_SIZE);



		/* Config audio fifo */

		acp_fifo_addr = ACP_SRAM_PTE_OFFSET +

				(rtd->num_pages * 8) + CAPTURE_FIFO_ADDR_OFFSET;

		rv_writel(acp_fifo_addr, rtd->acp3x_base +

			  mmACP_BT_RX_FIFOADDR);

		rv_writel(FIFO_SIZE, rtd->acp3x_base + mmACP_BT_RX_FIFOSIZE);

	}



	/* Enable  watermark/period interrupt to host */

	rv_writel(BIT(BT_TX_THRESHOLD) | BIT(BT_RX_THRESHOLD),

		  rtd->acp3x_base + mmACP_EXTERNAL_INTR_CNTL);

}



static int acp3x_dma_open(struct snd_pcm_substream *substream)

{

	int ret = 0;



	struct snd_pcm_runtime *runtime = substream->runtime;

	struct snd_soc_pcm_runtime *prtd = substream->private_data;

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,

								    DRV_NAME);

	struct i2s_dev_data *adata = dev_get_drvdata(component->dev);



	struct i2s_stream_instance *i2s_data = kzalloc(sizeof(struct i2s_stream_instance),

						       GFP_KERNEL);

	if (!i2s_data)

		return -EINVAL;



	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)

		runtime->hw = acp3x_pcm_hardware_playback;

	else

		runtime->hw = acp3x_pcm_hardware_capture;



	ret = snd_pcm_hw_constraint_integer(runtime,

					    SNDRV_PCM_HW_PARAM_PERIODS);

	if (ret < 0) {

		dev_err(component->dev, "set integer constraint failed\n");

		return ret;

	}



	if (!adata->play_stream && !adata->capture_stream)

		rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);



	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)

		adata->play_stream = substream;

	else

		adata->capture_stream = substream;



	i2s_data->acp3x_base = adata->acp3x_base;

	runtime->private_data = i2s_data;

	return 0;

}



static int acp3x_dma_hw_params(struct snd_pcm_substream *substream,

			       struct snd_pcm_hw_params *params)

{

	int status;

	u64 size;

	struct snd_dma_buffer *dma_buffer;

	struct page *pg;

	struct snd_pcm_runtime *runtime = substream->runtime;

	struct i2s_stream_instance *rtd = runtime->private_data;



	if (!rtd)

		return -EINVAL;



	dma_buffer = &substream->dma_buffer;

	size = params_buffer_bytes(params);

	status = snd_pcm_lib_malloc_pages(substream, size);

	if (status < 0)

		return status;



	memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));

	pg = virt_to_page(substream->dma_buffer.area);

	if (pg) {

		rtd->pg = pg;

		rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);

		config_acp3x_dma(rtd, substream->stream);

		status = 0;

	} else {

		status = -ENOMEM;

	}

	return status;

}



static snd_pcm_uframes_t acp3x_dma_pointer(struct snd_pcm_substream *substream)

{

	u32 pos = 0;

	struct i2s_stream_instance *rtd = substream->runtime->private_data;



	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)

		pos = rv_readl(rtd->acp3x_base +

			       mmACP_BT_TX_LINKPOSITIONCNTR);

	else

		pos = rv_readl(rtd->acp3x_base +

			       mmACP_BT_RX_LINKPOSITIONCNTR);



	if (pos >= MAX_BUFFER)

		pos = 0;



	return bytes_to_frames(substream->runtime, pos);

}



static int acp3x_dma_new(struct snd_soc_pcm_runtime *rtd)

{

	return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,

						     SNDRV_DMA_TYPE_DEV,

						     NULL, MIN_BUFFER,

						     MAX_BUFFER);

}



static int acp3x_dma_hw_free(struct snd_pcm_substream *substream)

{

	return snd_pcm_lib_free_pages(substream);

}



static int acp3x_dma_mmap(struct snd_pcm_substream *substream,

			  struct vm_area_struct *vma)

{

	return snd_pcm_lib_default_mmap(substream, vma);

}



static int acp3x_dma_close(struct snd_pcm_substream *substream)

{

	struct snd_soc_pcm_runtime *prtd = substream->private_data;

	struct i2s_stream_instance *rtd = substream->runtime->private_data;

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,

								    DRV_NAME);

	struct i2s_dev_data *adata = dev_get_drvdata(component->dev);



	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)

		adata->play_stream = NULL;

	else

		adata->capture_stream = NULL;



	/* Disable ACP irq, when the current stream is being closed and

	 * another stream is also not active.

	 */

	if (!adata->play_stream && !adata->capture_stream)

		rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB);

	kfree(rtd);

	return 0;

}



static struct snd_pcm_ops acp3x_dma_ops = {

	.open = NULL,

	.close = NULL,

	.ioctl = NULL,

	.hw_params = NULL,

	.hw_free = NULL,

	.pointer = NULL,

	.mmap = NULL,

	.open = acp3x_dma_open,

	.close = acp3x_dma_close,

	.ioctl = snd_pcm_lib_ioctl,

	.hw_params = acp3x_dma_hw_params,

	.hw_free = acp3x_dma_hw_free,

	.pointer = acp3x_dma_pointer,

	.mmap = acp3x_dma_mmap,

};



struct snd_soc_dai_ops acp3x_dai_i2s_ops = {

sound/soc/amd/raven/acp3x.h

+20 −0
Original line number Diff line number Diff line
@@ -13,6 +13,26 @@ 
#define ACP3x_POWER_OFF_IN_PROGRESS 0x03

#define ACP3x_SOFT_RESET__SoftResetAudDone_MASK	0x00010001



#define ACP_SRAM_PTE_OFFSET	0x02050000

#define PAGE_SIZE_4K_ENABLE 0x2

#define MEM_WINDOW_START	0x4000000

#define PLAYBACK_FIFO_ADDR_OFFSET 0x400

#define CAPTURE_FIFO_ADDR_OFFSET  0x500



#define PLAYBACK_MIN_NUM_PERIODS    2

#define PLAYBACK_MAX_NUM_PERIODS    8

#define PLAYBACK_MAX_PERIOD_SIZE    16384

#define PLAYBACK_MIN_PERIOD_SIZE    4096

#define CAPTURE_MIN_NUM_PERIODS     2

#define CAPTURE_MAX_NUM_PERIODS     8

#define CAPTURE_MAX_PERIOD_SIZE     16384

#define CAPTURE_MIN_PERIOD_SIZE     4096



#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)

#define MIN_BUFFER MAX_BUFFER

#define FIFO_SIZE 0x100

#define DMA_SIZE 0x40



static inline u32 rv_readl(void __iomem *base_addr)

{

	return readl(base_addr - ACP3x_PHY_BASE_ADDRESS);

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