dt-bindings: dma: Convert stm32 DMAMUX bindings to json-schema

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/st,stm32-dmamux.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 DMA MUX (DMA request router) bindings

maintainers:

  - Amelie Delaunay <amelie.delaunay@st.com>

allOf:

  - $ref: "dma-router.yaml#"

properties:

  "#dma-cells":

    const: 3

  compatible:

    const: st,stm32h7-dmamux

  reg:

    maxItems: 1

  clocks:

    maxItems: 1

  resets:

    maxItems: 1

required:

  - compatible

  - reg

  - dma-masters

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/stm32mp1-clks.h>

    #include <dt-bindings/reset/stm32mp1-resets.h>

    dma-router@40020800 {

      compatible = "st,stm32h7-dmamux";

      reg = <0x40020800 0x3c>;

      #dma-cells = <3>;

      dma-requests = <128>;

      dma-channels = <16>;

      dma-masters = <&dma1 &dma2>;

      clocks = <&timer_clk>;

    };

...

STM32 DMA MUX (DMA request router)

Required properties:

- compatible:	"st,stm32h7-dmamux"

- reg:		Memory map for accessing module

- #dma-cells:	Should be set to <3>.

		First parameter is request line number.

		Second is DMA channel configuration

		Third is Fifo threshold

		For more details about the three cells, please see

		stm32-dma.txt documentation binding file

- dma-masters:	Phandle pointing to the DMA controllers.

		Several controllers are allowed. Only "st,stm32-dma" DMA

		compatible are supported.

Optional properties:

- dma-channels : Number of DMA requests supported.

- dma-requests : Number of DMAMUX requests supported.

- resets: Reference to a reset controller asserting the DMA controller

- clocks: Input clock of the DMAMUX instance.

Example:

/* DMA controller 1 */

dma1: dma-controller@40020000 {

	compatible = "st,stm32-dma";

	reg = <0x40020000 0x400>;

	interrupts = <11>,

		     <12>,

		     <13>,

		     <14>,

		     <15>,

		     <16>,

		     <17>,

		     <47>;

	clocks = <&timer_clk>;

	#dma-cells = <4>;

	st,mem2mem;

	resets = <&rcc 150>;

	dma-channels = <8>;

	dma-requests = <8>;

};

/* DMA controller 1 */

dma2: dma@40020400 {

	compatible = "st,stm32-dma";

	reg = <0x40020400 0x400>;

	interrupts = <56>,

		     <57>,

		     <58>,

		     <59>,

		     <60>,

		     <68>,

		     <69>,

		     <70>;

	clocks = <&timer_clk>;

	#dma-cells = <4>;

	st,mem2mem;

	resets = <&rcc 150>;

	dma-channels = <8>;

	dma-requests = <8>;

};

/* DMA mux */

dmamux1: dma-router@40020800 {

	compatible = "st,stm32h7-dmamux";

	reg = <0x40020800 0x3c>;

	#dma-cells = <3>;

	dma-requests = <128>;

	dma-channels = <16>;

	dma-masters = <&dma1 &dma2>;

	clocks = <&timer_clk>;

};

/* DMA client */

usart1: serial@40011000 {

	compatible = "st,stm32-usart", "st,stm32-uart";

	reg = <0x40011000 0x400>;

	interrupts = <37>;

	clocks = <&timer_clk>;

	dmas = <&dmamux1 41 0x414 0>,

	       <&dmamux1 42 0x414 0>;

	dma-names = "rx", "tx";

};