Unverified Commit 0b6f7014 authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
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arm64: dts: allwinner: h6: add USB3 device nodes



Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
a custom PHY.

Add device tree nodes for them.

Signed-off-by: default avatarOndrej Jirman <megous@megous.com>
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
Reviewed-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
parent 1e92dbea
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+32 −0
Original line number Diff line number Diff line
@@ -570,6 +570,38 @@
			status = "disabled";
		};

		dwc3: dwc3@5200000 {
			compatible = "snps,dwc3";
			reg = <0x05200000 0x10000>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_XHCI>,
				 <&ccu CLK_BUS_XHCI>,
				 <&rtc 0>;
			clock-names = "ref", "bus_early", "suspend";
			resets = <&ccu RST_BUS_XHCI>;
			/*
			 * The datasheet of the chip doesn't declare the
			 * peripheral function, and there's no boards known
			 * to have a USB Type-B port routed to the port.
			 * In addition, no one has tested the peripheral
			 * function yet.
			 * So set the dr_mode to "host" in the DTSI file.
			 */
			dr_mode = "host";
			phys = <&usb3phy>;
			phy-names = "usb3-phy";
			status = "disabled";
		};

		usb3phy: phy@5210000 {
			compatible = "allwinner,sun50i-h6-usb3-phy";
			reg = <0x5210000 0x10000>;
			clocks = <&ccu CLK_USB_PHY1>;
			resets = <&ccu RST_USB_PHY1>;
			#phy-cells = <0>;
			status = "disabled";
		};

		ehci3: usb@5311000 {
			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
			reg = <0x05311000 0x100>;