Unverified Commit 0b546bbe authored Sep 09, 2020 by Brad Bishop Committed by Mark Brown Sep 17, 2020

spi: fsi: Fix clock running too fast



Use a clock divider tuned to a 200MHz FSI bus frequency (the maximum). Use
of the previous divider at 200MHz results in corrupt data from endpoint
devices. Ideally the clock divider would be calculated from the FSI clock,
but that would require some significant work on the FSI driver. With FSI
frequencies slower than 200MHz, the SPI clock will simply run slower, but
safely.

Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20200909222857.28653-3-eajames@linux.ibm.com


Signed-off-by: Mark Brown <broonie@kernel.org>

parent 2b3cef0f

drivers/spi/spi-fsi.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -350,7 +350,7 @@ static int fsi_spi_transfer_init(struct fsi_spi *ctx)
		u64 status = 0ULL;
		u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE \|
		SPI_FSI_CLOCK_CFG_SCK_NO_DEL \|
		FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 4);
		FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19);

		end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS);
		do {

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