pinctrl: at91: Enable slewrate by default on SAM9X60 (0b329285) · Commits · 戴 / test

On SAM9X60, slewrate should be enabled on pins with a switching frequency below 50Mhz. Since most of our pins do not exceed this value, we enable slewrate by default. Pins with a switching value that exceeds 50Mhz will have to explicitly disable slewrate. This patch changes the ABI. However, the slewrate macros are only used by SAM9X60 and, at this moment, there are no device-tree files available for this platform. Suggested-by:

Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by:

Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20191101092031.24896-1-codrin.ciubotariu@microchip.com Acked-by:

Ludovic Desroches <ludovic.desroches@microchip.com> Reviewed-by:

Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by:

Linus Walleij <linus.walleij@linaro.org>

drivers/pinctrl/pinctrl-at91.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -85,8 +85,8 @@ enum drive_strength_bit {
		DRIVE_STRENGTH_SHIFT)

		enum slewrate_bit {
		SLEWRATE_BIT_DIS,
		SLEWRATE_BIT_ENA,
		SLEWRATE_BIT_DIS,
		};

		#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
		@@ -669,7 +669,7 @@ static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
		{
		unsigned int tmp;

		if (setting < SLEWRATE_BIT_DIS \|\| setting > SLEWRATE_BIT_ENA)
		if (setting < SLEWRATE_BIT_ENA \|\| setting > SLEWRATE_BIT_DIS)
		return;

		tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);

include/dt-bindings/pinctrl/at91.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -27,8 +27,8 @@
		#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
		#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)

		#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9)
		#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9)
		#define AT91_PINCTRL_SLEWRATE_ENA (0x0 << 9)
		#define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9)

		#define AT91_PIOA 0
		#define AT91_PIOB 1

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